Variable frequency clock output circuit and apparatus, motor driving apparatus, and image forming apparatus

A variable frequency clock output circuit, comprising:

• a target value register which stores a target value corresponding to an arbitrarily set target frequency;
• an increase/decrease value register which stores an arbitrarily set increase/decrease value;
• an adder-subtractor which has an input portion into which a current output value is inputted and outputs a calculation result obtained by adding/subtracting the increase/decrease value stored in the increase/decrease value register to/from the current output value inputted into the input portion based on an addition/subtraction instruction signal;
• a comparator which compares an output value of the adder-subtractor to the target value stored in the target value register, and outputs an addition/subtraction instruction signal to the adder-subtractor until the output value of the adder-subtractor and the target value coincide;
• and
• a clock generator which outputs a clock signal having a frequency proportional to the output value of the adder-subtractor,
• wherein the clock generator includes an adder and a selector,
• wherein the adder adds a value of higher-order bits excluding a fractional part of bits from the output value of the adder-subtractor, to an output value of the selector,
• wherein the selector selects and outputs either the output value of the adder or fixed data, and
• wherein the clock generator outputs a value of highest-order bits of the output value of the selector as a clock signal.

A variable frequency clock output circuit, comprising:

• a target value register which stores a target value corresponding to an arbitrarily set target frequency;
• an increase/decrease value register which stores an arbitrarily set increase/decrease value;
• an adder-subtractor which has an input portion into which a current output value is inputted and outputs a calculation result obtained by adding/subtracting the increase/decrease value stored in the increase/decrease value register to/from the current output value inputted into the input portion based on an addition/subtraction instruction signal;
• a comparator which compares an output value of the adder-subtractor to the target value stored in the target value register, and outputs an addition/subtraction instruction signal to the adder-subtractor until the output value of the adder-subtractor and the target value coincide;
• a clock generator which outputs a clock signal having a frequency proportional to the output value of the adder-subtractor;
• and
• a multi-stage FIFO register for the target value register and the increase/decrease value register,
• wherein a target value and an increase/decrease value are set to the target value register and the increase/decrease value register, respectively from the FIFO register, every time the output value of the adder-subtractor and the target value coincide with each other as a result of the comparison by the comparator.

A variable frequency clock output apparatus in which a plurality of variable frequency clock output circuits are integrally modularized,

• wherein each of the variable frequency clock output circuits comprises:
• a target value register which stores a target value corresponding to an arbitrarily set target frequency;
• an increase/decrease value register which stores an arbitrarily set increase/decrease value, wherein the increase/decrease value is a fractional value;
• an adder-subtractor which has an input portion into which a current output value is inputted and outputs a calculation result obtained by adding/subtracting the increase/decrease value stored in the increase/decrease value register to/from the current output value inputted into the input portion based on an addition/subtraction instruction signal, wherein the output value of the adder-subtractor includes a fractional value;
• a comparator which compares an output value of the adder-subtractor to the target value stored in the target value register, and outputs an addition/subtraction instruction signal to the adder-subtractor until the output value of the adder-subtractor and the target value coincide, wherein the comparator compares a value of higher-order bits excluding the fractional part of bits from the output value of the adder-subtractor, to the target value, and a value of bits including the fractional part of bits from the current output value of the adder-subtractor, is inputted into the input portion of the adder-subtractor;
• and
• a clock generator which outputs a clock signal having a frequency proportional to the output value of the adder-subtractor.

An image forming apparatus, comprising:

• one or a plurality of paper conveyance motors;
• a motor driving apparatus which drives the paper conveyance motors;
• and
• a printer which prints on a paper conveyed by the paper conveyance motors,
• wherein the motor driving apparatus is equipped with a variable frequency clock output circuit and a driving circuit which drives a motor based on a clock outputted from the clock output circuit, and
• wherein the variable frequency clock output circuit comprises:
• a target value register which stores a target value corresponding to an arbitrarily set target frequency;
• an increase/decrease value register which stores an arbitrarily set increase/decrease value, wherein the increase/decrease value is a fractional value;
• an adder-subtractor which has an input portion into which a current output value is inputted and outputs a calculation result obtained by adding/subtracting the increase/decrease value stored in the increase/decrease value register to/from the current output value inputted into the input portion based on an addition/subtraction instruction signal, wherein the output value of the adder-subtractor includes a fractional value;
• a comparator which compares an output value of the adder-subtractor to the target value stored in the target value register, and outputs an addition/subtraction instruction signal to the adder-subtractor until the output value of the adder-subtractor and the target value coincide, wherein the comparator compares a value of higher-order bits excluding the fractional part of bits from the output value of the adder-subtractor, to the target value, and a value of bits including the fractional part of bits from the current output value of the adder-subtractor, is inputted into the input portion of the adder-subtractor;
• and
• a clock generator which outputs a clock signal having a frequency proportional to the output value of the adder-subtractor.

An image forming apparatus, comprising:

• one or a plurality of paper conveyance motors;
• a motor driving apparatus which drives the paper conveyance motors;
• and
• a printer which prints on a paper conveyed by the paper conveyance motors, wherein the motor driving apparatus is equipped with a variable frequency clock output circuit and a driving circuit which drives a motor based on a clock outputted from the clock output circuit, and
• wherein the variable frequency clock output circuit comprises:
• a target value register which stores a target value corresponding to an arbitrarily set target frequency;
• an increase/decrease value register which stores an arbitrarily set increase/decrease value;
• an adder-subtractor which has an input portion into which a current output value is inputted and outputs a calculation result obtained by adding/subtracting the increase/decrease value stored in the increase/decrease value register to/from the current output value inputted into the input portion based on an addition/subtraction instruction signal;
• a comparator which compares an output value of the adder-subtractor to the target value stored in the target value register, and outputs an addition/subtraction instruction signal to the adder-subtractor until the output value of the adder-subtractor and the target value coincide;
• and
• a clock generator which outputs a clock signal having a frequency proportional to the output value of the adder-subtractor,
• wherein a CPU sets the target value and the increase/decrease value that are appropriate for a paper conveyance sequence, onto the target registers and the increase/decrease registers in one or a plurality of variable frequency clock output circuits, respectively;
• a detector which detects a paper conveyance status,
• wherein the CPU sets the target value and the increase/decrease value that are appropriate for the detected paper conveyance status.

A variable frequency clock output apparatus in which a plurality of variable frequency clock output circuits are integrally modularized,

• wherein each of the variable frequency clock output circuits comprises:
• a target value register which stores a target value corresponding to an arbitrarily set target frequency;
• an increase/decrease value register which stores an arbitrarily set increase/decrease value;
• an adder-subtractor which has an input portion into which a current output value is inputted and outputs a calculation result obtained by adding/subtracting the increase/decrease value stored in the increase/decrease value register to/from the current output value inputted into the input portion based on an addition/subtraction instruction signal;
• a comparator which compares an output value of the adder-subtractor to the target value stored in the target value register, and outputs an addition/subtraction instruction signal to the adder-subtractor until the output value of the adder-subtractor and the target value coincide;
• and
• a clock generator which outputs a clock signal having a frequency proportional to the output value of the adder-subtractor, wherein the clock generator includes an adder and a selector, the adder adds a value of higher-order bits excluding a fractional part of bits from the output value of the adder-subtractor, to an output value of the selector, the selector selects and outputs either the output value of the adder or fixed data, and the clock generator outputs a value of highest-order bits of the output value of the selector as a clock signal.

A variable frequency clock output apparatus in which a plurality of variable frequency clock output circuits are integrally modularized,

• wherein each of the variable frequency clock output circuits comprises:
• a target value register which stores a target value corresponding to an arbitrarily set target frequency;
• an increase/decrease value register which stores an arbitrarily set increase/decrease value;
• a multi-stage FIFO register for the target value register and the increase/decrease value register,
• an adder-subtractor which has an input portion into which a current output value is inputted and outputs a calculation result obtained by adding/subtracting the increase/decrease value stored in the increase/decrease value register to/from the current output value inputted into the input portion based on an addition/subtraction instruction signal;
• a comparator which compares an out/Put value of the adder-subtractor to the target value stored in the target value register, and outputs an addition/subtraction instruction signal to the adder-subtractor until the output value of the adder-subtractor and the target value coincide;
• and
• a clock generator which outputs a clock signal having a frequency proportional to the output value of the adder-subtractor,
• wherein a target value and an increase/decrease value are set to the target value register and the increase/decrease value register, respectively from the FIFO register, every time the output value of the adder-subtractor and the target value coincide with each other as a result of the comparison by the comparator.

An image forming apparatus, comprising:

• one or a plurality of paper conveyance motors;
• a motor driving apparatus which drives the paper conveyance motors;
• and
• a printer which prints on a paper conveyed by the paper conveyance motors,
• wherein the motor driving apparatus is equipped with a variable frequency clock output circuit and a driving circuit which drives a motor based on a clock outputted from the clock output circuit, and
• wherein the variable frequency clock output circuit comprises:
• a target value register which stores a target value corresponding to an arbitrarily set target frequency;
• an increase/decrease value register which stores an arbitrarily set increase/decrease value;
• an adder-subtractor which has an input portion into which a current output value is inputted and outputs a calculation result obtained by adding/subtracting the increase/decrease value stored in the increase/decrease value register to/from the current output value inputted into the input portion based on an addition/subtraction instruction signal;
• a comparator which compares an output value of the adder-subtractor to the target value stored in the target value register, and outputs an addition/subtraction instruction signal to the adder-subtractor until the output value of the adder-subtractor and the target value coincide;
• and
• a clock generator which outputs a clock signal having a frequency proportional to the output value of the adder-subtractor,
• wherein the clock generator includes an adder and a selector, the adder adds a value of higher-order bits excluding a fractional part of bits from the output value of the adder-subtractor, to an output value of the selector, the selector selects and outputs either the output value of the adder or fixed data, and the clock generator outputs a value of highest-order bits of the output value of the selector as a clock signal.

An image forming apparatus, comprising:

• one or a plurality of paper conveyance motors;
• a motor driving apparatus which drives the paper conveyance motors;
• and
• a printer which prints on a paper conveyed by the paper conveyance motors,
• wherein the motor driving apparatus is equipped with a variable frequency clock output circuit and a driving circuit which drives a motor based on a clock outputted from the clock output circuit, and
• wherein the variable frequency clock output circuit comprises:
• a target value register which stores a target value corresponding to an arbitrarily set target frequency;
• an increase/decrease value register which stores an arbitrarily set increase/decrease value;
• a multi-stage FIFO register for the target value register and the increase/decrease value register,
• an adder-subtractor which has an input portion into which a current output value is inputted and outputs a calculation result obtained by adding/subtracting the increase/decrease value stored in the increase/decrease value register to/from the current output value inputted into the input portion based on an addition/subtraction instruction signal;
• a comparator which compares an output value of the adder-subtractor to the target value stored in the target value register, and outputs an addition/subtraction instruction signal to the adder-subtractor until the output value of the adder-subtractor and the target value coincide;
• and
• a clock generator which outputs a clock signal having a frequency proportional to the output value of the adder-subtractor,
• wherein a target value and an increase/decrease value are set to the target value register and the increase/decrease value register, respectively from the FIFO register, every time the output value of the adder-subtractor and the target value coincide with each other as a result of the comparison by the comparator.