Methods for designing semiconductor device with dynamic array section

A method for designing a semiconductor chip having one or more functionally interfaced dynamic array sections, comprising:

• defining a dynamic array section grid on a portion of the chip, wherein the dynamic array section grid is defined by a virtual network of perpendicular gridlines projected upon the portion of the chip;
• defining boundaries of a dynamic array section, wherein each of the defined boundaries of the dynamic array section aligns with a gridline of the dynamic array section grid, wherein the dynamic array section represents a portion of the chip defined according to a dynamic array architecture;
• defining one or more diffusion regions to be formed within a substrate portion of the dynamic array section;
• defining a plurality of levels of the chip above the substrate portion within the dynamic array section by,
• defining a virtual grate for each of the plurality of levels, the virtual grate defined by a framework of parallel lines spaced at a substantially constant pitch, such that the framework of parallel lines that define the virtual grate for a particular level are oriented to be substantially perpendicular to the framework of parallel lines that define the virtual grate for either a level above or a level below the particular level, and
• defining a number of linear conductive features along the framework of lines that define the virtual grate in each of the plurality of levels, wherein some of the lines that define the virtual grates in the plurality of levels each have defined thereon multiple linear conductive features having proximate ends separated by a gap, wherein each gap is defined to maintain a substantially uniform distance between proximate ends of linear conductive features within a portion of a given level of the chip within the dynamic array section,
• wherein each of the number of linear conductive features is defined to be devoid of a substantial change in direction relative to the line of the virtual grate along which the linear conductive feature is defined;
• and
• operating a computer to store a resulting definition of the dynamic array section as computer readable code on a computer readable storage medium.

A method for designing a dynamic array section of a semiconductor chip, comprising:

• defining one or more diffusion regions to be formed within a substrate portion of the chip;
• defining a plurality of levels of the dynamic array section above the substrate portion, each level defined to include linear conductive features arranged along a virtual grate associated with the level, the virtual grate of each level defined by a framework of parallel lines spaced at a substantially constant pitch, the virtual grates in adjacent levels oriented to be perpendicular to each other;
• laying out a full-length linear conductive feature along a full length of a number of lines of each virtual grate of each level;
• and
• segmenting some of the full-length linear conductive features into multiple linear conductive segments, the segmenting of a given full-length linear conductive feature into multiple linear conductive segments performed by placing one or more gaps along the given full-length linear conductive feature, wherein gaps placed within a region of a given level are uniformly defined,
• wherein a first portion of the linear conductive segments are defined to form conductive elements of an electronic circuit, and a remaining portion of the linear conductive segments are defined to support manufacturing of the first portion and do not form conductive elements of the electronic circuit,
• wherein each of the number of linear conductive segments is defined to be devoid of a substantial change in direction relative to the line of the virtual grate along which the linear conductive segment is laid out;
• and
• operating a computer to store a resulting definition of the dynamic array section as computer readable code on a computer readable storage medium.