Semiconductor device and associated layouts having transistors formed from six linear conductive segments with intervening diffusion contact restrictions

An integrated circuit device as recited in 2, wherein a region within the gate electrode level between the gate electrode of the third transistor of the first transistor type and the gate electrode of the fourth transistor of the first transistor type is devoid of a conductive structure that physically contacts an underlying diffusion region, and

• wherein the third and fourth transistors of the first transistor type are formed to share a second diffusion region.

An integrated circuit device as recited in 2, wherein a region within the gate electrode level between the gate electrode of the third transistor of the second transistor type and the gate electrode of the fourth transistor of the second transistor type is devoid of a conductive structure that physically contacts an underlying diffusion region, and

• wherein the third and fourth transistors of the second transistor type are formed to share a second diffusion region.

An integrated circuit device as recited in 2, wherein a region within the gate electrode level between the gate electrode of the first transistor of the second transistor type and the gate electrode of the second transistor of the second transistor type is devoid of a conductive structure that physically contacts an underlying diffusion region, and

• wherein the first and second transistors of the second transistor type are formed to share a second diffusion region.

An integrated circuit device as recited in 5, wherein a region within the gate electrode level between the gate electrode of the third transistor of the first transistor type and the gate electrode of the fourth transistor of the first transistor type is devoid of a conductive structure that physically contacts an underlying diffusion region, and

• wherein the third and fourth transistors of the first transistor type are formed to share a third diffusion region.

An integrated circuit device as recited in 6, wherein a region within the gate electrode level between the gate electrode of the third transistor of the second transistor type and the gate electrode of the fourth transistor of the second transistor type is devoid of a conductive structure that physically contacts an underlying diffusion region, and

• wherein the third and fourth transistors of the second transistor type are formed to share a fourth diffusion region.

An integrated circuit device as recited in 7, wherein a region within the gate electrode level between the gate electrode of the second transistor of the first transistor type and the gate electrode of the third transistor of the first transistor type includes at least one conductive structure that physically contacts a fifth diffusion region.

An integrated circuit device as recited in 8, wherein the second and third transistors of the first transistor type are formed to share the fifth diffusion region.

An integrated circuit device as recited in 8, wherein a region within the gate electrode level between the gate electrode of the second transistor of the second transistor type and the gate electrode of the third transistor of the second transistor type includes at least one conductive structure that physically contacts a sixth diffusion region.

An integrated circuit device as recited in 10, wherein the second and third transistors of the second transistor type are formed to share the sixth diffusion region.

An integrated circuit device as recited in 11, wherein the second and third transistors of the first transistor type are formed to share the fifth diffusion region.

An integrated circuit device as recited in 2, wherein the region of the gate electrode level includes five or more adjacently positioned linear conductive segments, wherein the five or more adjacently positioned linear conductive segments are formed such that their lengths extend in the first direction, wherein the five or more adjacently positioned linear conductive segments are formed to have a substantially equal centerline-to-centerline spacing between each pair of adjacently positioned linear conductive segments as measured perpendicular to the first direction.

An integrated circuit device as recited in 2, wherein each of the first, second, third, and fourth transistors of the first transistor type is defined to have a respective first dimension as measured in the first direction,

• wherein the first dimension of the second transistor of the first transistor type is greater than the first dimension of the third transistor of the first transistor type.

An integrated circuit device as recited in 14, wherein the first dimension of the first transistor of the first transistor type is substantially equal to the first dimension of the second transistor of the first transistor type, and

• wherein the first dimension of the fourth transistor of the first transistor type is substantially equal to the first dimension of the third transistor of the first transistor type.

An integrated circuit device as recited in 14, wherein each of the first, second, third, and fourth transistors of the second transistor type is defined to have a respective first dimension as measured in the first direction,

• wherein the first dimension of the second transistor of the second transistor type is greater than the first dimension of the third transistor of the second transistor type.

An integrated circuit device as recited in 16, wherein the first dimension of the first transistor of the second transistor type is substantially equal to the first dimension of the second transistor of the second transistor type, and

• wherein the first dimension of the fourth transistor of the second transistor type is substantially equal to the first dimension of the third transistor of the second transistor type.

An integrated circuit device as recited in 2, further comprising:

• an interconnect level region defined above the gate electrode level region, wherein the interconnect level region includes conductive structures formed to extend in a linear manner in the first direction over the gate electrode level region.

An integrated circuit device as recited in 18, wherein the conductive structures within the interconnect level region include at least two adjacently positioned conductive structures that extend in a parallel manner in the first direction over the gate electrode level region.

An integrated circuit device as recited in 19, wherein the gate electrode level region includes adjacently positioned linear conductive segments separated by a substantially equal centerline-to-centerline spacing, wherein the at least two adjacently positioned conductive structures within the interconnect level are separated by a centerline-to-centerline spacing substantially equal to the centerline-to-centerline spacing between adjacently positioned linear conductive segments within the gate electrode level region.

An integrated circuit device as recited in 2, further comprising:

• a diffusion level defined below the gate electrode level, wherein the diffusion level includes diffusion regions of a first type that form part of the first, second, third, and fourth transistors of the first transistor type, and wherein the diffusion level includes diffusion regions of a second type that form part of the first, second, third, and fourth transistors of the second transistor type,
• wherein the diffusion level includes a first non-active region between either of the first, second, third, or fourth transistors of the first transistor type and a neighboring transistor of the first transistor type.

An integrated circuit device as recited in 21, wherein the gate electrode level region includes adjacently positioned linear conductive segments separated by a substantially equal centerline-to-centerline spacing, wherein a size of the first non-active region is less than the centerline-to-centerline spacing between adjacently positioned linear conductive segments within the gate electrode level region.

An integrated circuit device as recited in 21, wherein the diffusion level includes a second non-active region between either of the first, second, third, or fourth transistors of the second transistor type and a neighboring transistor of the second transistor type.

An integrated circuit device as recited in 23, wherein the gate electrode level region includes adjacently positioned linear conductive segments separated by a substantially equal centerline-to-centerline spacing, wherein a size of the second non-active region is less than the centerline-to-centerline spacing between adjacently positioned linear conductive segments within the gate electrode level region.

An integrated circuit device as recited in 2, further comprising:

• a diffusion level defined below the gate electrode level, wherein the diffusion level includes diffusion regions of a first type that form part of the first, second, third, and fourth transistors of the first transistor type, and wherein the diffusion level includes diffusion regions of a second type that form part of the first, second, third, and fourth transistors of the second transistor type,
• wherein the diffusion level includes a first non-active region formed below a portion of an area extending between the sixth linear conductive segment and a first neighboring linear conductive segment within the gate electrode level region.

An integrated circuit device as recited in 25, wherein the first neighboring linear conductive segment within the gate electrode level region is formed over the first non-active region.

An integrated circuit device as recited in 25, wherein the first neighboring linear conductive segment within the gate electrode level region forms an gate electrode of a transistor device.

An integrated circuit device as recited in 25, wherein the diffusion level includes a second non-active region formed below a portion of an area extending between the first linear conductive segment and a second neighboring linear conductive segment within the gate electrode level region.

An integrated circuit device as recited in 28, wherein the second neighboring linear conductive segment within the gate electrode level region is formed over the second non-active region.

An integrated circuit device as recited in 28, wherein the second neighboring linear conductive segment within the gate electrode level region forms a gate electrode of a transistor device.