Method of manufacturing semiconductor chip using laser light and plasma dicing

A semiconductor chip manufacturing method in which a semiconductor chip containing a plurality of integrated circuits formed in a plurality of regions segmented by a plurality of scribe lines and containing a plurality of test patterns formed in said scribe lines is divided by a plasma etching process so as to manufacture individual semiconductor chips with respect to each of the integrated circuits, said semiconductor chip manufacturing method is comprising:

• a sheet adhering step for adhering a protection sheet which constitutes a mask in said plasma etching process onto a front plane of said semiconductor wafer, on which said integrated circuits have been formed, and further, for adhering a holding sheet onto a rear plane of said semiconductor wafer, said holding sheet being employed so as to hold the individual semiconductor chips when under divided condition;
• a test pattern removing step in which laser light is irradiated from the side of said protection sheet along the scribe lines with respect to said semiconductor wafer on which said protection sheet has been adhered, such that only a predetermined width of said protection sheet on said scribe lines is removed so as to form said mask, and also, said test patterns are removed in combination with a front plane layer of said semiconductor wafer;
• a preliminary plasma etching process for enlarging an opening width of an opening portion of said protection sheet removed by said laser light;
• a plasma dicing step in which a portion within said semiconductor wafer is plasma-etched after said test pattern removing step, such that a damaged layer produced by irradiating the laser light is removed, and also, said semiconductor wafer is divided with respect to each of said individual integrated circuits, wherein said portion corresponds to said removed protection sheet having the predetermined width and;
• a protection sheet removing step for removing said protection sheet from the front plane of said semiconductor wafer after said plasma dicing step.