Substrate for semiconductor device and manufacturing method thereof

A semiconductor package comprising:

• a substrate comprising a single layer dielectric layer, a plurality of conductive lands formed inside of the dielectric layer at a bottom surface of the dielectric layer, wherein the dielectric layer comprises a plurality of recesses at the bottom surface of the dielectric layer, the conductive lands being formed inside of the recesses, and a plurality of electrically conductive patterns formed at a top surface of the dielectric layer and connected to the plurality of conductive lands, wherein a plurality of bonding pads is formed at the electrically conductive patterns;
• a solder mask covering the dielectric layer and the electrically conductive patterns and having a plurality of openings, the bonding pads being located within the openings and being spaced apart from the solder mask so that portions of the top surface of the dielectric layer around the bonding pads are exposed through the openings;
• a semiconductor die attached to a top surface of the substrate and connected to the electrically conductive patterns;
• an encapsulant for encapsulating the top surface of the substrate and the semiconductor die;
• and
• a plurality of solder balls fused to the conductive lands of the substrate, wherein each solder ball of the plurality of solder balls extends into only a single respective recess of the plurality of recesses, wherein the conductive lands comprise:
• a copper layer;
• and
• a gold layer on the copper layer, the solder balls being fused to the gold layer.

A substrate for a semiconductor package, comprising:

• a metal carrier of a planar plate;
• a plurality of conductive lands on a surface of the carrier, wherein the conductive lands comprise a copper layer, a gold layer, another copper layer in order;
• a dielectric layer on the surface of the carrier covering the conductive lands;
• a plurality of electrically conductive patterns on a surface of the dielectric layer electrically connected to the conductive lands;
• and
• a solder mask on surfaces of the dielectric layer and the electrically conductive patterns, a predetermined area of each conductive pattern being exposed to outside through openings of the solder mask.

A semiconductor package comprising:

• a substrate comprising a single layer dielectric layer, a plurality of conductive lands formed inside of the dielectric layer at a bottom surface of the dielectric layer, wherein the dielectric layer comprises a plurality of recesses at the bottom surface of the dielectric layer, the conductive lands being formed inside of the recesses, and a plurality of electrically conductive patterns formed at a top surface of the dielectric layer and connected to the plurality of conductive lands, wherein a plurality of bonding pads is formed at the electrically conductive patterns;
• a solder mask covering the dielectric layer and the electrically conductive patterns and having a plurality of openings, the bonding pads being located within the openings and being spaced apart from the solder mask so that portions of the top surface of the dielectric layer around the bonding pads are exposed through the openings;
• a semiconductor die attached to a top surface of the substrate and connected to the electrically conductive patterns, wherein the semiconductor die is connected to top surfaces of the bonding pads by conductive wires;
• an encapsulant for encapsulating the top surface of the substrate and the semiconductor die, wherein the encapsulant encapsulates the conductive wires, the top and side surfaces of the bonding pads, and the portions of the top surface of the dielectric layer around the bonding pads exposed through the openings;
• and
• a plurality of solder balls fused to the conductive lands of the substrate, wherein each solder ball of the plurality of solder balls extends into only a single respective recess of the plurality of recesses.