Method for separately optimizing spacer width for two or more transistor classes using a recess spacer integration
AssigneeFreescale Semiconductor, Inc.
InventorAnadi Srivastava
Life of this patent
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Abstract
A method for making a semiconductor device is disclosed. In accordance with the method, a semiconductor structure is provided which includes (a) a substrate (203), (b) first and second gate electrodes (219) disposed over the substrate, each of the first and second gate electrodes having first and second sidewalls, and (c) first (223) and second (225) sets of spacer structures disposed adjacent to the first and second gate electrodes, respectively. A first layer of photoresist (231) is then disposed over the structure such that the first set of spacer structures is exposed and the second set of spacer structures is covered, after which the first set of spacer structures is partially etched.
Claims18
A method for making a semiconductor device, comprising:
- providing a semiconductor structure comprising (a) a substrate, (b) first and second gate electrodes disposed over the substrate, and (c) first and second sets of spacer structures disposed adjacent to said first and second gate electrodes, respectively, wherein each of said first and second sets of spacer structures comprises a first and second spacer disposed on opposing sides of one of said first and second gate electrodes, wherein said a topmost surface of said first set of spacer structures is coplanar with said first gate electrode, and wherein a topmost surface of said second set of spacer structures is coplanar with said second gate electrode;
- disposing a first layer of photoresist over the semiconductor structure such that the first set of spacer structures is exposed and the second set of spacer structures is covered;
- partially etching the first set of spacer structures;
- disposing a second layer of photoresist over the semiconductor structure such that the second set of spacer structures is exposed and the first set of spacer structures is covered;
- and
- partially etching the second set of spacer structures.
A method for making a semiconductor device, comprising:
- providing a semiconductor structure comprising (a) a substrate, (b) first, second and third gate electrodes disposed over the substrate, and (c) first, second and third sets of spacer structures disposed adjacent to said first, second and third gate electrodes, respectively, wherein each of said first, second and third sets of spacer structures comprises a first and second spacer disposed on opposing sides of one of said first, second and third gate electrodes wherein said a topmost surface of said first set of spacer structures is coplanar with said first gate electrode, and wherein a topmost surface of said second set of spacer structures is coplanar with said second gate electrode;
- disposing a first layer of photoresist over the semiconductor structure such that the first set of spacer structures is exposed and the second set of spacer structures is covered;
- partially etching the first set of spacer structures;
- disposing a second layer of photoresist over the semiconductor structure such that the second set of spacer structures is exposed and the first set of spacer structures is covered;
- and
- partially etching the second set of spacer structures.
Dependencies are inferred from the claim text.