Matrix modeling of parallel data structures to facilitate data encoding and/or jittery signal generation
AssigneeMicron Technology, Inc.
InventorTimothy M. Hollis
Life of this patent
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AssigneeMicron Technology, Inc.
InventorTimothy M. Hollis
Estimating the term…
A computer-implementable method comprises a matrix-based approach to generating in parallel a plurality of realistic simulatable signal vectors, which vectors include the addition of amplitude noise and/or timing jitter and encoding. Each channel in a parallel bus can be populated in a matrix, with each row comprising ideal voltage values for the channel, and the columns comprising bits of the sequence of voltage values for that channel. Encoding can be employed to modify the data in the matrix. Amplitude noise and/or timing jitter can then be applied to each channel (row) in the matrix. This modifies the time basis from a bit basis as used in the matrix to a time-step basis. With such modification accomplished, each row in the matrix can be transformed into simulatable vector, which vectors can then be simulated in parallel to test, the robustness of the parallel bus of which the channels are part.
A method implementable in a computer system for generating a plurality of simulatable vectors, comprising:
A method implementable in a computer system for generating a plurality of simulatable vectors, comprising:
A method implementable in a computer system for simulating the operation of a parallel bus, comprising:
A method implementable in a computer system for simulating the operation of a parallel bus, comprising:
Dependencies are inferred from the claim text.