Method and apparatus for providing secure intellectual property cores for a programmable logic device
AssigneeXilinx, Inc.
InventorsJay T. Young, Jeffrey M. Mason
Life of this patent
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Abstract
Method and apparatus for providing secure intellectual property (IP) cores for a programmable logic device (PLD) are described. An aspect of the invention relates to a method of securely distributing an IP core for PLDs. A circuit design is generated for the IP core, the circuit design being re-locatable in a programmable fabric for PLDs. The circuit design is encoded to produce at least one partial configuration bitstream. Implementation data is generated for utilizing the IP core as a reconfigurable module in top-level circuit designs. The at least one partial configuration bitstream and the implementation data are delivered to users of the PLDs.
Claims20
A computer-implemented method of securely distributing an intellectual property (IP) core for programmable devices, comprising:
- generating a circuit design for the IP core using a computer, the circuit design being re-locatable among a plurality of implementation areas of a programmable fabric for the programmable devices;
- encoding the circuit design using the computer to produce at least one partial configuration bitstream;
- generating implementation data using the computer for utilizing the IP core as a reconfigurable module in top-level circuit designs;
- and
- delivering the at least one partial configuration bitstream and the implementation data to users of the programmable devices.
A computer-implemented method of utilizing a secure intellectual property (IP) core in a programmable device, comprising:
- obtaining at least one partial configuration bitstream and implementation data for the IP core, the at least one partial configuration bitstream encoding at least one implementation of a circuit design for the IP core, the circuit design being re-locatable among a plurality of implementation areas of a programmable fabric of the programmable device;
- implementing a top-level circuit design having the IP core using a computer where, based on the implementation data, the IP core is located in the programmable fabric as a reconfigurable model and the top-level circuit design is interfaced with the reconfigurable model;
- generating a design configuration bitstream for the top-level circuit design using the computer;
- and
- merging a selected one of the at least one partial configuration bitstream with the design configuration bitstream using the computer.
Apparatus for utilizing a secure intellectual property (IP) core in a programmable device, comprising:
- a database configured to store at least one partial configuration bitstream and implementation data for the IP core, the at least one partial configuration bitstream encoding at least one implementation of a circuit design for the IP core, the circuit design being re-locatable among a plurality of implementation areas of a programmable fabric of the programmable device;
- a place-and-route tool configured to implement a top-level circuit design having the IP core where, based on the implementation data, the IP core is located in the programmable fabric as a reconfigurable module and the top-level circuit design is interfaced with the reconfigurable module;
- and
- a bitstream generator configured to generate a design configuration bitstream for the top-level circuit design and merge a selected one of the at least one partial configuration bitstream with the design configuration bitstream.
Dependencies are inferred from the claim text.