Layout data reduction for use with electronic design automation tools

A computer system for implementing a method used to provide semiconductor device design data for viewing, comprising:

• a computer processor coupled to a computer monitor and a memory;
• wherein the computer processor is programmed for:
• receiving a schematic of a semiconductor device design, the schematic having a plurality of schematic devices;
• receiving a netlist;
• receiving a layout data comprising a three dimensional physical translation of the plurality of schematic devices of the semiconductor device design, wherein the three dimensional physical translation comprises a grid pitch, an offset of polygon structures, and a hierarchy;
• dividing the layout data into a plurality of subsets of layout data, wherein each subset of layout data comprises only a portion of the three dimensional physical translation;
• correlating each of the plurality of subsets of layout data such that the grid pitch and the offset of polygon structures of the three dimensional physical translation are maintained subsequent to the data correlation;
• cross mapping each subset of layout data with the netlist, using the computer processor, to correlate leads of the three dimensional physical translation associated with each subset of layout data to leads of the schematic devices;
• and
• accessing at least one, but less than all, of the plurality of subsets of layout data to provide a view of the accessed subsets of layout data on the computer monitor, while a remainder of the plurality of subsets of layout data remains correlated but unaccessed.