Wire mapping for programmable logic devices
AssigneeLattice Semiconductor Corporation
InventorsByung-Kyoo Kang, Toshikazu Endo
Life of this patent
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Abstract
Various techniques for referencing components of a programmable logic device (PLD) are provided. In one example, a method of referencing wires of a routing graph of a PLD is provided. The routing graph comprises a plurality of routing graph wires and a plurality of routing graph switches corresponding to components of the PLD. The method includes maintaining a plurality of master tiles comprising a plurality of master wires and a plurality of master switches corresponding to the routing graph wires and the routing graph switches, respectively. The method also includes identifying a first one of the routing graph wires. The method further includes mapping the first routing graph wire to a second one of the routing graph wires using at least one of the master wires.
Claims15
A computer-implemented method of referencing wires of a routing graph of a programmable logic device (PLD), wherein the routing graph comprises a plurality of routing graph wires and a plurality of routing graph switches corresponding to components of the PLD, the method comprising:
- maintaining in a computing system a plurality of master tiles comprising a plurality of master wires and a plurality of master switches corresponding to the routing graph wires and the routing graph switches, respectively;
- identifying in the computing system a first one of the routing graph wires;
- and
- mapping in the computing system the first routing graph wire to a second one of the routing graph wires using at least one of the master wires, wherein the first routing graph wire is a segmented wire of the PLD, the second routing graph wire is a composite wire of the PLD, and the composite wire comprises the segmented wire,
- wherein the mapping comprises:
- mapping the first routing graph wire to a master wire;
- mapping the first master wire to master switch;
- Identifying a segmented wire of the PLD connected to the master switch;
- mapping the segmented wire of the PLD to a second master wire;
- and
- mapping the second master wire to the second routing graph wire,
- wherein the second routing graph wire is connected to the first routing graph wire through at least one of the routing graph switches.
A computing system comprising:
- one or more processors;
- and
- one or more memories adapted to store a plurality of computer readable instructions which when executed by the one or more processors are adapted to cause the system to perform a method of referencing wires of a routing graph of a programmable logic device (PLD), wherein the routing graph comprises a plurality of routing graph wires and a plurality of routing graph switches corresponding to components of the PLD, the method comprising:
- maintaining a plurality of master tiles comprising a plurality of master wires and a plurality of master switches corresponding to the routing graph wires and the routing graph switches, respectively,
- identifying a first one of the routing graph wires, and
- mapping the first routing graph wire to a second one of the routing graph wires using at least one of the master wires, wherein the first routing graph wire is a segmented wire of the PLD, the second routing graph wire is a composite wire of the PLD, and the composite wire comprises the segmented wire,
- wherein the mapping comprises:
- mapping the first routing graph wire to a first one of the master wires;
- mapping the first master wire to at least one of the master switches;
- identifying a segmented wire of the PLD connected to the master switch;
- mapping the segmented wire of the PLD to a second master wire;
- and
- mapping the second master wire to the second routing graph wire,
- wherein the second routing graph wire is connected to the first routing graph wire through at least one of the routing graph switches.
A non-transitory computer readable medium on which is stored a computer program which when executed by a computing system performs a method of referencing wires of a routing graph of a programmable logic device (PLD), wherein the routing graph comprises a plurality of routing graph wires and a plurality of routing graph switches corresponding to components of the PLD, the method comprising:
- maintaining in a computing system a plurality of master tiles comprising a plurality of master wires and a plurality of master switches corresponding to the routing graph wires and the routing graph switches, respectively;
- identifying in the computing system a first one of the routing graph wires;
- and
- mapping in the computing system the first routing graph wire to a second one of the routing graph wires using at least one of the master wires, wherein the first routing graph wire is a segmented wire of the PLD, the second routing graph wire is a composite wire of the PLO, and the composite wire comprises the segmented wire,
- wherein the mapping comprises:
- mapping the first routing graph wire to a master wire;
- mapping the first master wire to master switch;
- Identifying a segmented wire of the PLD connected to the master switch;
- mapping the segmented wire of the PLO to a second master wire;
- and
- mapping the second master wire to the second routing graph wire.
- wherein the second routing graph wire is connected to the first routing graph wire through at least one of the routing graph switches.
Dependencies are inferred from the claim text.