US 7,890,904 B2 · Estimating jitter in a clock tree of a circuit and synthesizing a jitter-aware and skew-aware clock tree

Abstract

In one embodiment, a method for computing jitter in a clock tree includes dividing a clock tree into a plurality of stages and computing jitter in one or more of the stages according to a model of at least a portion of a circuit associated with the clock tree. The model includes a representation of each source of jitter in the circuit. The method also includes, to compute jitter associated with a path or a pair of paths in the clock tree, statistically combining the jitter in each of the stages of the path or the pair of paths in the clock tree with each other. In one embodiment, to efficiently compute jitter and to achieve zero clock skew, a method synthesizes a symmetrical clock tree of a circuit in which corresponding stages in all paths from a root of the clock tree to sinks of the clock tree exhibit approximate electrical equivalence to each other.

Claims13

Dependent claims

A method comprising:

dividing by one or more computer systems a clock tree into a plurality of stages;
computing by the one or more computer systems jitter in one or more of the stages according to a model of at least a portion of a circuit associated with the clock tree, the model comprising a representation of each source of jitter in the circuit;
and
to compute jitter associated with a path or a pair of paths in the clock tree, statistically combining by the one or more computer systems the jitter in each of the stages of the path or the pair of paths in the clock tree with each other.

1 more element

Dependencies are inferred from the claim text.

Estimating jitter in a clock tree of a circuit and synthesizing a jitter-aware and skew-aware clock tree

Life of this patent

Estimating jitter in a clock tree of a circuit and synthesizing a jitter-aware and skew-aware clock tree

Life of this patent

Abstract

Claims13