Method and system for formal verification of an electronic circuit design

A system for formal verification of an electronic circuit design, said electronic circuit performing at least one arithmetic multiplication operation, wherein a netlist of said circuit design is provided, and wherein said circuit design is based on a Booth encoding for the multiplication operations, said system comprising:

• a processor;
• a data bus coupled to said processor;
• and
• a computer-usable medium embodying computer code, said computer-usable medium being coupled to said data bus, said computer program code comprising instructions executable by said processor and configured for:
• providing a reference design on a word level which is based on an abstract language specification comprising an arithmetic and a structural description for a netlist of said reference design, wherein said specification further comprises a partial product generator that determines a chosen Booth-encoding and computes the partial product with respect to this encoding, and wherein said specification comprises an adder tree that sums all partial products, and wherein the adder networks of both the reference design and the circuit design have the same topology, and wherein the Booth encoding of said reference design is equal to the Booth encoding of said circuit design;
• adding correction signals for sign conversion of negative values to said reference design and said circuit design;
• converting said reference design into a reference gate netlist;
• performing an equivalence check between said reference gate netlist and said netlist of said circuit design;
• extracting an adder network from the reference design;
• checking arithmetic functions the adder network can perform, wherein said reference design is corrected if said extracted adder network does not perform the correct arithmetic function;
• when generating said reference gate netlist as a gate level reference, each call to a function of the partial product generator causing an instantiation of a corresponding generic VHDL entity;
• generating an arithmetic bit level description of said reference design by expanding the Booth-encoded partial products into weighted sums of bitwise multiplications;
• and
• deciding on the correctness of said circuit design based on the results of the equivalence check between the reference gate netlist and the netlist of the circuit design and the arithmetic function check of the extracted adder network.

A non-transitory computer-usable medium embodying computer program code for formal verification of an electronic circuit design, said electronic circuit performing at least one arithmetic multiplication operation, wherein a netlist of said circuit design is provided, and wherein said circuit design is based on a Booth encoding for the multiplication operations, said computer program code comprising computer executable instructions configured for:

• providing a reference design on a word level which is based on an abstract language specification comprising an arithmetic and a structural description for a netlist of said reference design, wherein said specification further comprises a partial product generator that determines a chosen Booth-encoding and computes the partial product with respect to this encoding, and wherein said specification comprises an adder tree that sums all partial products, and wherein the adder networks of both the reference design and the circuit design have the same topology, and wherein the Booth encoding of said reference design is equal to the Booth encoding of said circuit design;
• adding correction signals for sign conversion of negative values to said reference design and said circuit design;
• converting said reference design into a reference gate netlist;
• performing an equivalence check between said reference gate netlist and said netlist of said circuit design;
• extracting an adder network from the reference design;
• checking arithmetic functions the adder network can perform, wherein said reference design is corrected if said extracted adder network does not perform the correct arithmetic function;
• when generating said reference gate netlist as a gate level reference, each call to a function of the partial product generator causing an instantiation of a corresponding generic VHDL entity;
• generating an arithmetic bit level description of said reference design by expanding the Booth-encoded partial products into weighted sums of bitwise multiplications;
• and
• deciding on the correctness of said circuit design based on the results of the equivalence check between the reference gate netlist and the netlist of the circuit design and the arithmetic function check of the extracted adder network.