Method and system for verifying the equivalence of digital circuits
AssigneeInternational Business Machines Corporation
InventorsTobias Gemmeke, Jens Leenstra, Nicolas Maeding, Hari Mony
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AssigneeInternational Business Machines Corporation
InventorsTobias Gemmeke, Jens Leenstra, Nicolas Maeding, Hari Mony
Estimating the term…
The automatic verification of designs of digital circuits for their equivalence, wherein logic designs implemented in different hardware description languages (HDLs) and different design methodologies are compared. The designs (Code A, Code B) are modified by adding special wrappers (Wrapper A, Wrapper B), and used to equalize the timing of pairs of selected input signals and selected output signals of the logic designs. The wrappers drive certain signals of the designs that are not relevant for actual comparison, such signals including clock signals, clock control signals, scan-path signals, scan-path control signals, and reset signals. In a preferred embodiment, HDL descriptions of logic designs are analyzed. Based on this analysis, the wrappers are implemented as changes to the HDL descriptions. In another embodiment, RTL and/or gate-level netlists are analyzed and modified.
A method for verifying equivalent logic circuits respectively having different clocking configurations, different types of storage elements, and different descriptive languages, the method comprising:
A non-transitory program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for verifying equivalent logic circuits having different clocking configurations, different types of storage elements, and different descriptive languages, the program of instructions executable comprising:
Dependencies are inferred from the claim text.