Variable clocked scan test improvements
AssigneeIntellectual Ventures I LLC
InventorsLaurence H. Cooke, Bulent I. Dervisoglu
Life of this patent
Estimating the term…
Abstract
Addition of specific test logic may improve the level of test vector compression achieved from existing variable scan test logic. Methods for determining the compressed vectors' states, given the desired uncompressed vectors' values may be used, and techniques for selectively enabling test or other features on a chip by inserting the proper code or codes into the chip may further be used. Techniques may be used to incorporate and apply various types of reset operations to multiple strings of variable scan test logic, as may methods to minimize the test vector compression computation time.
Claims14
A test structure in an integrated circuit (IC), the test structure comprising:
- key enable logic configured to accept a key input and to generate a plurality of select signals;
- and
- a plurality of scan-chain segments, wherein a first one of the plurality of scan-chain segments is configured to receive a primary serial input, and wherein each subsequent one of the plurality of scan-chain segments is configured to receive an input from an exclusive-or function of the primary serial input, gated by at least one of the select signals and an output of a previous one of the plurality of scan-chain segments;
- wherein the test structure is configured such that enabling a greater number of select signals corresponds to more compressed test vectors being enabled for use in testing the IC.
A structure for an integrated circuit (IC), the structure comprising:
- a plurality of logic blocks, wherein each logic block corresponds to a feature of the IC and is configured to be enabled by a select line;
- and
- key enable logic configured to drive a select line used to enable a respective one of the plurality of logic blocks;
- wherein each of the select lines is configured to enable a feature of the IC when a selected subset of bits for a key inputted into the key enable logic is equivalent to a set of preset bit values corresponding to a particular select line.
A method of fabricating an integrated circuit (IC), the method comprising:
- providing key enable logic configured to accept a key input and to generate a plurality of select signals;
- and
- providing a structure configured to receive and to respond to the select signals, wherein the structure is selected from a group consisting of:
- a plurality of scan-chain segments, wherein a first one of the plurality of scan-chain segments is configured to receive a primary serial input, wherein each subsequent one of the plurality of scan-chain segments is configured to receive an input from an exclusive-or function of the primary serial input, gated by at least one of the select signals and an output of a previous one of the plurality of scan-chain segments, and wherein enabling a greater number of select signals corresponds to more compressed test vectors being for use in testing the IC;
- and
- a plurality of logic blocks, wherein each logic block corresponds to a feature of the IC and is configured to be enabled by a select line, and wherein each of the select lines is configured to enable a feature of the IC when a selected subset of bits for a key inputted into the key enable logic is equivalent to a set of preset bit values corresponding to a particular select line.
Dependencies are inferred from the claim text.