US 7,890,894 B2 · Phase abstraction for formal verification

Abstract

A method for functional verification includes transforming an original multiphase circuit design into a phase-abstracted circuit design by identifying cyclical (repetitive) signals in the multiphase circuit design, determining a number of simulation phases for the multiphase circuit design, unwinding the multiphase circuit design by the number of phases to create an unwound design, and then applying logic reduction techniques to the unwound design using the clock-like signals to reduce (simplify) the logic in the unwound design by eliminating unused/unnecessary registers, inputs, outputs, and logic. The resulting phase-abstracted design can then be processed much more efficiently by functional verification engines than the original multiphase circuit design due to the reduced number of registers/inputs.

Claims12

Dependent claims

A system for processing a multiphase circuit design, the system including a non-transitory computer-readable medium encoded with logic comprising:

logic for applying a set of initial conditions to the multiphase circuit design using three-valued simulation, the three-valued simulation using a set of values consisting of 0, 1, and X, wherein the value X represents an unknown state;
logic for applying a series of clock cycles to the multiphase circuit design while all inputs to the multiphase circuit design are held at the value X;
logic for monitoring simulation state vectors for a set of registers in the multiphase circuit design to identify an end-cycle state vector that is identical to a start-cycle state vector, the start-cycle state vector being generated prior to the end-cycle state vector;
and
logic for deriving a series of repeating state vectors for the set of registers in the multiphase circuit design based on a series of simulation state vectors between the start-cycle state vector and the end-cycle state vector.

2 more elements

A non-transitory computer-readable medium encoded with a program for causing a computer to process a multiphase circuit design, the program comprising:

instructions for causing the computer to apply a set of initial conditions to the multiphase circuit design using three-valued simulation, the three-valued simulation using a set of values consisting of 0, 1, and X, wherein the value X represents an unknown state;
instructions for causing the computer to apply a series of clock cycles to the multiphase circuit design while all inputs to the multiphase circuit design are held at the value X;
instructions for causing the computer to monitor simulation state vectors for a set of registers in the multiphase circuit design to identify an end-cycle state vector that is identical to a start-cycle state vector, the start-cycle state vector being generated prior to the end-cycle state vector;
and
instructions for causing the computer to derive a series of repeating state vectors for the set of registers in the multiphase circuit design based on a series of simulation state vectors between the start-cycle state vector and the end-cycle state vector.

2 more elements

Dependencies are inferred from the claim text.

Phase abstraction for formal verification

Life of this patent

Phase abstraction for formal verification

Life of this patent

Abstract

Claims12