US 7,890,892 B2Granted

Balanced and bi-directional bit line paths for memory arrays with programmable memory cells

AssigneeInternational Business Machines Corporation

InventorsJohn K. De Brosse, Mark C. H. Lamorey

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Abstract

Disclosed is a design structure of an improved large scale memory system and, more particularly, an improved memory system that incorporates an array of memory cells that are subjected to minimal location dependent power variations and that, optionally, allows for bi-directional random access of millions of bits. Specifically, the system architecture provides a consistent amount of bit line resistance in the write and read paths to each memory cell in the array, independent of position, in order to minimize variations in power delivery to the cells and, thereby, allow for optimal cell distributions. The system architecture further allows current to pass in either direction through the cells in order to minimize element electro-migration and, thereby, extend memory cell life.

Claims15

Dependent claims

A system comprising:

a non-transitory computer readable medium storing a design structure for a memory system;
and
a machine for manufacturing said memory system, said machine comprising instructions and executing said instructions so as to retrieve said design structure and produce said memory system based on said design structure such that said memory system comprises:
a plurality of memory cells;
a plurality of bit lines, each of said memory cells being coupled between two of said bit lines;
and a plurality of isolation devices coupled to said bit lines and configured to establish a plurality of different current pathways through said bit lines and said memory cells, each of said different current pathways comprising a first segment of a first bit line, a second segment of a second bit line different from said first bit line and a memory cell connected in series between said first segment and said second segment, said first segment having a first resistance and said second segment having a second resistance such that a total resistance of each of said current different current pathways is approximately equal for all memory cell locations within said memory system.

3 more elements

A system comprising:

a non-transitory computer readable medium storing a design structure for a memory system;
and
a machine for manufacturing said memory system, said machine comprising instructions and executing said instructions so as to retrieve said design structure and produce said memory system based on said design structure such that said memory system comprises:
a plurality of memory cells;
a plurality of bit lines, each of said memory cells being coupled between two of said bit lines;
a plurality of isolation devices coupled to said bit lines and configured to establish a plurality of different bi-directional current pathways through said bit lines and said memory cells, each of said different bi-directional current pathways comprising a first segment of a first bit line, a second segment of a second bit line different from said first bit line and a memory cell connected in series between said first bit line and said second bit line such that a total resistance of each of said current pathways is approximately equal for all memory cell locations within said memory system;
and
a first decode circuit connected to a first end of each of said current pathways and a second decode circuit connected to a second end of each of said current pathways, said first decode circuit directing a current in a first direction through said memory cells and said second decode circuit directing said current in a second direction, different than said first direction, through said memory cells.

5 more elements

A system comprising:

a non-transitory computer readable medium storing a design structure for a memory system;
and
a machine for manufacturing said memory system, said machine comprising instructions and executing said instructions so as to retrieve said design structure and produce said memory system based on said design structure such that said memory system comprises:
a plurality of memory cells;
a plurality of bit lines, each of said memory cells being coupled to two of said bit lines and comprising:
an access transistor comprising:
a first source/drain region coupled to one of said two of said bit lines;
and
a second source/drain region;
and
a programmable resistor comprising:
a first terminal coupled to said second source/drain region;
and
a second terminal coupled to another of said two of said bit lines;
and
a plurality of isolation devices coupled to said bit lines and configured to establish current pathways through said bit lines and said memory cells such that a resistance of each of said current pathways is approximately equal for all memory cell locations within said system;
a first decode circuit connected to a first end of each of said current pathways and a second decode circuit connected to a second end of each of said current pathways, wherein said first decode circuit is adapted to direct a write current in a first direction through said memory cells and wherein said second decode circuit is adapted to direct said write current in a second direction through said memory cells;
and
a controller connected to said first decode circuit and said second decode circuit and adapted to periodically switch said write current between said first direction and said second direction.

16 more elements

Dependencies are inferred from the claim text.