Integrated MPE-FEC RAM for DVB-H receivers

A Multi-Protocol Encapsulator Forward Error Connection (MPE-FEC) memory chip for use in a Digital Video Broadcasting over Handheld (DVB-H) receiver, said memory chip comprising:

• a Transport-stream packet de-multiplexer (TS demux);
• a Reed-Solomon (RS) decoder;
• a system bus;
• a random access memory (RAM) unit that simultaneously interfaces to said TS demux, said RS decoder, and said system bus through time-multiplexing;
• and
• a demodulator positioned on a same silicon chip as said RAM unit, said TS demux said RS decoder, and said system bus,
• wherein said RAM unit (i) accesses multiple-words per clock cycle, and (ii) caches write and read accesses to reduce memory access from said TS demux and said system bus, and
• wherein said RAM unit clocks at a speed higher than an interfacing data-path to increase an effective throughput of said RAM unit.

A method of processing video internet protocol (IP) datagrams in a Digital Video Broadcasting over Handheld (DVB-H) receiver, wherein said DVB-H receiver comprises a Multi-Protocol Encapsulator Forward Error Connection (MPE-FEC) memory chip comprising a Transport-stream (TS) packet de-multiplexer (TS demux);

• a Reed-Solomon (RS) decoder;
• a system bus;
• and a random access memory (RAM) unit that simultaneously interfaces to said TS demux, said RS decoder, and said system bus through time-multiplexing, said method comprising:
• configuring said RAM unit to access multiple-words per cycle and cache read and write accesses to said RAM unit to reduce memory access from said TS demux and said system bus;
• and
• clocking said RAM unit at a speed higher than an interfacing data-path to increase an effective throughput of said RAM unit.