Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorsHaruki Toda, Toshiaki Edahiro
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Abstract
A memory device includes an error detection and correction system with an error correcting code over Galois field GF(2n), which has an operation circuit configured to execute addition/subtraction with modulo 2n−1, wherein the operation circuit includes first and second operation parts for performing addition/subtraction with modulo M and modulo N (where, M and N are integers, which are prime with each other as being obtained by factorizing 2n−1), the first and second operation parts being for performing addition/subtraction simultaneously in parallel with each other to output an operation result of the addition/subtraction with modulo 2n−1, and wherein the first and second operation parts each includes an adder circuit.
Claims15
A semiconductor memory device comprising an error detection and correction system with an error correcting code over Galois field GF(2n), wherein
- the error detection and correction system includes an operation circuit configured to execute addition/subtraction with modulo 2n−1, and wherein
- the operation circuit includes a first operation part for performing addition/subtraction with modulo M and a second operation part for performing addition/subtraction with modulo N (where M and N are integers, which are prime with each other as being obtained by factorizing 2n−1, the first and second operation parts being for performing addition/subtraction simultaneously in parallel with each other to output an operation result of the addition/subtraction with modulo 2n−1, and wherein
- the first and second operation parts each comprises an adder circuit, which is configured to output a sum of two numbers to-be-added as a remainder of modulus thereof, and wherein
- the adder circuit includes a correction circuit for adding a complement to the sum when it becomes modulus number thereof or more.
A semiconductor memory device comprising a cell array with electrically rewritable and non-volatile memory cells arranged therein, and an error detection and correction system, which is correctable up to 2-bit errors for read out data of the cell array by use of a BCH code over Galois field GF(256), wherein
- the error detection and correction system comprises:
- an encoding part configured to generate check bits to be written into the cell array together with to-be-written data;
- a syndrome operating part configured to execute syndrome operation for read out data of the cell array;
- an error location searching part configured to search error locations in the read out data based on the operation result of the syndrome operating part;
- and
- an error correcting part configured to invert an error bit in the read out data detected in the error location searching part, and output it, and wherein
- the error location searching part includes an operation circuit configured to execute index addition/subtraction with modulo 255, and wherein
- the operation circuit includes a first adder circuit for performing addition/subtraction with modulo 17 and a second adder circuit for performing addition/subtraction with modulo 15, which perform addition/subtraction simultaneously in parallel with each other to output an operation result of the index addition/subtraction with modulo 255, and wherein
- the first and second adder circuits each comprises a correction circuit for adding a complement to the sum when it becomes modulus number thereof or more.
Dependencies are inferred from the claim text.