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US 7,890,836 B2Granted
Method and apparatus of cache assisted error detection and correction in memory
AssigneeIntel Corporation
InventorSean Eilert
Life of this patent
Estimating the term…
Abstract
A memory and a method of correcting and detecting an error in a codeword of a memory are presented. The method includes detection and correction of an error in a bit of the codeword by an error deception and correction engine, storing error correction information of the error in a cache. In the second detection of the same error in the same bit the correction of the error is done based on the stored error correction information.
Claims7
A method of correcting and detecting one or more errors in a codeword stored in a memory comprising:
- accessing an address containing a first error in a main array of memory cells;
- detecting and correcting an error in a bit of a codeword of the accessed address;
- storing error correction information of the error in a an error cache Random Access Memory (RAM) and in a nonvolatile (NV) memory, wherein the error correction information includes at least an address of an error row, a symbol location in the error row and a correction value for a symbol containing the bit;
- and
- permanently repairing the main array of memory cells by downloading a repaired row from the NV memory, erasing the error row and writing the downloaded row at the address of the error row.
2 more elements
An apparatus comprising:
- an array of memory cells;
- an error detecting and correcting error engine to detect an error in a bit of a codeword and to generate error correction information for the bit of the codeword wherein, the error correction information includes at least an address of an error row, a symbol location in the error row and a correction value for a symbol containing the bit;
- an error cache random access memory (RAM) to store the error correction information of the detected error to be used to correct a further occurrence of the detected error in the bit of the codeword;
- a nonvolatile (NV) memory to store a backup of the error correction information;
- and
- a permanent repair algorithm to repair errors in the array of memory cells by downloading a repaired row from the NV memory and replacing a memory row containing a detected error with the downloaded repaired row.
3 more elements
Dependencies are inferred from the claim text.