Cyclic redundancy check circuit and communication system having the same for multi-channel communication

A communication system comprising:

• a plurality of storing units configured to store data in parallel;
• a cyclic redundancy check circuit configured to receive data output in parallel from the storing units and to generate cyclic redundancy check bits;
• and
• a transmission circuit configured to transmit data output in parallel from the storing units and the cyclic redundancy check bits through the multi-channel,
• wherein the cyclic redundancy check circuit comprises a bit generation circuit that generates the cyclic redundancy check bits that satisfy a cyclic redundancy check polynomial of a mono-channel serial communication system with respect to a first point in time, and that provides the cyclic redundancy check bits based upon data that is delayed from the first point in time by a number of clock cycles that correspond to the number of multi-channels.

A communication system comprising:

• a plurality of storing units configured to store parallel data that is received with first cyclic redundancy check bits through a multi-channel;
• a cyclic redundancy check circuit configured to receive the parallel data and to generate second cyclic redundancy check bits based on the parallel data;
• and
• a determination portion configured to determine the detection of an error by comparing the first cyclic redundancy check bits with the second cyclic redundancy check bits generated by the cyclic redundancy check circuit,
• wherein the cyclic redundancy check circuit comprises a bit generation circuit that generates the cyclic redundancy check bits that satisfy a cyclic redundancy check polynomial of a mono-channel serial communication system with respect to a first point in time, and that provides the cyclic redundancy check bits based upon data that is delayed from the first point in time by a number of clock cycles that correspond to the number of multi-channels.

A communication system comprising at least one of:

• a first cyclic redundancy check circuit configured to input parallel data and to generate first cyclic redundancy check bits based on the parallel data to be transmitted through a multi-channel;
• and
• a second cyclic redundancy check circuit configured to receive the parallel data received through a multi-channel and to generate second cyclic redundancy check bits based on the received parallel data
• wherein the first cyclic redundancy check circuit and the second cyclic redundancy check circuit each provide a bit generation circuit that generates the cyclic redundancy check bits that satisfy a cyclic redundancy check polynomial of a mono-channel serial communication system with respect to a first point in time, and that provides the cyclic redundancy check bits based upon data that is delayed from the first point in time by a number of clock cycles that correspond to the number of multi-channels.

A multi-channel serial communication system comprising:

• a cyclic redundancy check circuit configured to receive first and second channel data in parallel and to generate cyclic redundancy check bits according to a predetermined generation expression;
• and
• a transmission circuit configured to transmit the first and second channel data in parallel and the cyclic redundancy check bits in parallel through the two channels,
• wherein the cyclic redundancy check circuit provides a bit generation circuit that generates the cyclic redundancy check bits that satisfy a cyclic redundancy check polynomial of a mono-channel serial communication system with respect to a first point in time, and that provides the cyclic redundancy check bits based upon data that is delayed from the first point in time by a number of clock cycles that correspond to the number of multi-channels.

A multi-channel serial communication system comprising:

• a cyclic redundancy check circuit configured to receive first and second channel data in parallel and to generate cyclic redundancy check bits according to a predetermined generation expression;
• and
• a determination portion configured to determine the detection of an error by comparing first cyclic redundancy check bits received from a transmitting circuit with second cyclic redundancy check bits,
• wherein the cyclic redundancy check circuit provides a bit generation circuit that generates the cyclic redundancy check bits that satisfy a cyclic redundancy check polynomial of a mono-channel serial communication system with respect to a first point in time, and that provides the cyclic redundancy check bits based upon data that is delayed from the first point in time by a number of clock cycles that correspond to the number of multi-channels.