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US 7,890,832 B2Granted
Method for accuracy improvement allowing chip-by-chip measurement correction
AssigneeIntersil Americas Inc.
InventorRichard A. Dunipace
Life of this patent
Estimating the term…
Abstract
A method for allowing measurement corrections on a chip-by-chip basis. Error correction values are generated responsive to the input value to a circuit of the calibrated integrated circuit chip and to a measured value from the circuit of the calibrated integrated circuit chip. The error correction values are stored within an error correction table within a nonvolatile memory of the integrated circuit chip.
Claims8
A method for allowing measurement corrections on a chip by chip basis, comprising the steps of:
- applying a reference value to an input of a circuit of an integrated circuit chip;
- measuring an output value generated by the circuit of the integrated circuit chip responsive to the reference value;
- generating an offset error for the circuit by determining a difference between an analog equivalent of the output value and the reference value;
- applying an input value comprising a reduced percentage of full scale to the input of the integrated circuit chip;
- measuring a second output value responsive to the input value at the output of the integrated circuit chip;
- generating a gain error value for the output of the integrated circuit chip by subtracting the offset error from the second output value and dividing by the input value for the output of the integrated circuit chip;
- storing the offset error and the gain error in an error correction table within a non-volatile memory of the integrated circuit chip.
4 more elements
An integrated circuit chip, comprising:
- circuitry including an input for receiving a first input value for generating a first measurement value responsive to the first input value and for receiving a second input value for generating a second measurement value responsive to the second input value;
- a non-volatile memory;
- and
- an error correction table within the non-volatile memory for storing error correction values, the error correction values correcting at least one output of the second circuitry, wherein the error correction values further comprise an offset error generated by determining a difference between an analog equivalent of the first measurement value at an output of the second circuitry and the first input value applied to the input of the second circuitry and a gain error generated by subtracting the offset error at an output of the second circuitry from the second measurement value at the output of the second circuitry divided by the second input value at the input of the second circuitry.
1 more element
Dependencies are inferred from the claim text.