US 7,890,831 B2Granted

Processor test system utilizing functional redundancy

AssigneeGlobalfoundries Inc.

InventorsMichael L. Choate, Mark D. Nicol, Heather L. Hanson, Michael J. Borsch, Arthur M. Ryan, Chandrakant Pandya

Life of this patent

Estimating the term…

Loading patent…

Abstract

A system and method for testing a processor. The system includes a gold processor and a test processor, wherein the test processor is the device under test (DUT). The test processor and the gold processor are identical. A first memory is coupled to the gold processor by a first memory bus and a second memory, independent of the first, is coupled to the test processor by a second memory bus. The first and second memories are identical. A memory bus comparator coupled to the first and second memory buses compares memory bus signals generated by the gold and test processors, and selectively provide a first indication if a mismatch occurs. A peripheral bus comparator is also coupled to the gold and test processors, and compares downstream transactions generated by the gold and test processors and to provide a second indication if a peripheral bus comparison results in a mismatch.

Claims20

Dependent claims

A system for testing a processor, the system comprising:

a gold processor socket configured to receive a gold processor;
a test processor socket configured to receive a test processor, wherein the test processor is a device under test (DUT);
a first memory coupled to the gold processor socket via a first memory bus;
a second memory coupled to the test processor socket, via a second memory bus, wherein the first and second memories are independent of one another;
a memory bus comparator coupled to the first memory bus and the second memory bus, wherein the memory bus comparator is configured to, when the gold and test processors are present and operating in their respective sockets, compare memory signals generated by the gold processor to memory signals generated by the test processor and to provide a first indication if a memory bus comparison results in a mismatch;
a peripheral bus comparator coupled to the gold processor and the test processor socket, wherein the peripheral bus comparator is configured to, when the gold and test processors are present in their respective sockets, compare downstream transactions generated by the gold processor to downstream transactions generated by the test processor and to provide a second indication if a peripheral bus comparison results in a mismatch.

3 more elements

A method for testing a processor, the method comprising:

operating a gold processor, said operating the gold processor including:
generating and conveying memory signals to a first memory coupled to the gold processor via a first memory bus;
generating and conveying downstream transactions to a peripheral bus comparator;
operating a test processor, said operating the test processor including:
generating and conveying memory signals to a second memory coupled to the test processor via a second memory bus, wherein the first and second memories are independent of one another;
generating and conveying downstream transactions to a peripheral bus comparator;
comparing memory signals conveyed from the gold processor on the first memory bus to memory signals conveyed from the test processor on the second memory bus;
providing a signal that enables or disables a first indication of a mismatch between the memory signals;
providing the first indication if said comparing memory signals results in a mismatch when the first indication is enabled by the first signal;
comparing downstream transactions conveyed from the gold processor on the first peripheral bus to downstream transactions conveyed from the test processor on the second peripheral bus;
and
providing a second indication if said comparing downstream transactions results in a mismatch.

9 more elements

Dependencies are inferred from the claim text.