Built-in self-test using embedded memory and processor in an application specific integrated circuit
AssigneeMarvell International Technology Ltd.
InventorsRichard D. Taylor, Mark D. Montierth, Melvin D. Bodily, Gary Zimmerman, John D. Marshall
Life of this patent
Estimating the term…
Abstract
A test method for an ASIC uses an embedded processor in the ASIC to execute test routines from an embedded memory or an external memory. During ASIC production, the test routines can comprehensively test of the blocks of the ASIC without a complicated test pattern from test equipment. The test routines can also perform power-up tests in systems or end products containing the ASIC. Test selection, activation, and result output can be implement using a few terminals of the ASIC.
Claims22
An integrated circuit comprising:
- a processing core;
- and
- a memory containing:
- a first set of test routines that are executable by the processing core to test the integrated circuit, and
- a second set of test routines that are executable by the processing core to test the integrated circuit,
- wherein a control signal input to the integrated circuit controls whether the first set of test routines or the second set of test routines is executed by the processing core,
- wherein the control signal has a first state to indicate selection of the first set of test routines, and
- wherein the control signal has a second state to indicate selection of the second set of test routines.
A test method for an integrated circuit, the test method comprising:
- using a processing core in the integrated circuit to execute (i) a first set of test routines to test the integrated circuit or (ii) a second set of test routines to test the integrated circuit, the first set of test routines and the second set of test routines being stored in a memory of the integrated circuit;
- applying a control signal to the integrated circuit;
- and
- selecting the first set of test routines or the second set of test routines based on the control signal,
- wherein the control signal has a first state to indicate selection of the first set of test routines, and
- wherein the control signal has a second state to indicate selection of the second set of test routines.
An integrated circuit comprising:
- a processing core;
- a memory containing test routines that the processing core executes to test the integrated circuit, wherein the memory contains a first set of test routines and a second set of test routines, and wherein a control signal input to the integrated circuit controls whether the first set of test routines or the second set of test routines are executed;
- and
- an interface coupled to the processing core to permit activation of a first output signal indicating a test result from execution of the first set of test routines or the second set of test routines,
- wherein the control signal has a first state to indicate selection of the first set of test routines, and
- wherein the control signal has a second state to indicate selection of the second set of test routines.
Dependencies are inferred from the claim text.