Compressing test responses using a compactor
AssigneeMentor Graphics Corporation
InventorsJanusz Rajski, Jerzy Tyszer, Chen Wang, Grzegorz Mrugalski, Artur Pogiel
Life of this patent
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Abstract
The present disclosure describes embodiments of a compactor for compressing test results in an integrated circuit and methods for using and designing such embodiments. The disclosed compactors can be utilized, for example, as part of any scan-based design. Moreover, any of the disclosed compactors can be designed, simulated, and/or verified in a computer-executed application, such as an electronic-design-automation (“EDA”) software tool. Embodiments of a method for diagnosing faults in the disclosed compactor embodiments are also described.
Claims15
A method for testing an integrated circuit, comprising:
- capturing multiple test values in a scan chain of a circuit-under-test, the test values being associated with a circuit response to a test pattern;
- clocking the test values out of the scan chain and into a compactor;
- producing sets of two or more output values in the compactor, each set comprising all values produced in the compactor at least partially determined by a respective test value;
- and
- outputting at least one of the sets from the compactor over at least two clock cycles and before all of the test values captured in the scan chain have been clocked into the compactor.
A computer-readable medium storing computer-executable instructions which when executed by a computer system cause the computer system to perform a method, the method comprising:
- modifying a circuit design database to include circuit design information, the circuit design information defining a compactor that is configured to:
- capture multiple test values in a scan chain of a circuit-under-test, the test values being associated with a circuit response to a test pattern;
- clock the test values out of the scan chain and into the compactor;
- produce sets of two or more output values in the compactor each set comprising all values produced in the compactor at least partially determined by a respective test value;
- and
- output at least one of the sets from the compactor over at least two clock cycles and before all of the test values captured in the scan chain have been clocked into the compactor.
A system, comprising:
- means for capturing multiple test values in a scan chain of a circuit-under-test, the test values being associated with a circuit response to a test pattern;
- means for clocking the test values out of the scan chain and into a compactor;
- means for producing sets of two or more output values in the compactor, each set comprising all values produced in the compactor at least partially determined by a respective test value;
- and
- means for outputting at least one of the sets from the compactor over at least two clock cycles and before all of the test values captured in the scan chain have been clocked into the compactor.
Dependencies are inferred from the claim text.