Asynchronous communication apparatus using JTAG test data registers

A method of using an extendable IEEE 1149.1 Joint Test Action Group standard interface to provide an asynchronous protocol for bypassing test circuitry and bi-directionally communicating with functional circuitry, the method comprising:

• providing an integrated circuit having at least one function register and Joint Test Action Group standard test data register ring having a plurality of serial test data registers and corresponding parallel test data registers that include data bits, address bits to address the at least one function register and an ADDRESS VALID bit to indicate correctness of the address bits;
• and
• providing digital logic configured to control a direct transfer of data between the Joint Test Action Group standard test data register ring and the at least one function register, the digital logic including a DATA GOOD signal that includes a timing delay configured to facilitate the direct transfer of the data bits from the at least one Joint Test Action Group standard test data register and the at least one function register.

An apparatus for extending the IEEE 1149.1 Joint Test Action Group standard to provide an asynchronous protocol for bypassing test circuitry and bi-directionally communicating with functional circuitry, the apparatus comprising:

• an integrated circuit having at least one function register and at least one Joint Test Action Group standard test data register, wherein the at least one Joint Test Action Group standard test data register includes data bits for representing data to be written to or to be read from the at least one function register, address bits to address the at least one function register, and an ADDRESS VALID bit to indicate correctness of the address bits;
• and
• digital logic configured to control the direct transfer of data between the at least one Joint Test Action Group standard test data register and the at least one function register, wherein the digital logic is configured to generate a DATA GOOD signal that includes a timing delay configured to facilitate the transfer of the data bits from the at least one Joint Test Action Group standard test data register and the at least one function register.