Nonvolatile semiconductor memory system

An electrical package comprising:

• an external input portion to which compressed test data is loaded;
• an external output portion configured to output compacted test result;
• a first integrated circuit that is compatible with a compressed deterministic pattern test, the first integrated circuit including:
• a first input portion that is connected to the external input portion to receive the compressed test data;
• a first decompressor that is connected to a part of the first input portion to—decompress the compressed test data, and that outputs first test data;
• a first scan chain that is connected to the first decompressor to receive the first test data, and that outputs a first test result;
• a first compactor that is connected to the first scan chain to compact the first test result, and that outputs first compacted test result;
• a first selector that is connected to the part of the first input portion and the first decompressor to selectively output the first test data or the compressed test data as a first selector output;
• a second selector that is connected to the first compactor and the first selector to selectively output the first compacted test result or the first selector output as a second selector output;
• and
• a first output portion that is connected to the second selector and that outputs the second selector output as a first circuit output, a second integrated circuit that is non-compatible with the compressed deterministic pattern test, the second integrated circuit including:
• a second input portion that is connected to the first output portion to receive the first circuit output;
• a second scan chain that is connected to a part of the second input portion to receive the first test data, and that outputs a second test result;
• a third selector that is connected to the second scan chain and the part of the second input portion to selectively output the second test result or the first circuit output as a third selector output;
• a second output portion that is connected to the third selector, and that outputs the third selector output as a second circuit output, a third integrated circuit that is compatible with the compressed deterministic pattern test, the third integrated circuit including:
• a third input portion that is connected to the second output portion to receive the second circuit output;
• a third decompressor that is connected to a part of the third input portion to decompress the compressed test data, and that outputs third test data;
• a third scan chain that is connected to the third decompressor to receive the third test data and that outputs a third test result;
• a fourth selector that is connected to the third scan chain and the third input portion to selectively output the second test result or the third test result as a fourth selector output;
• a third compactor that is connected to the fourth selector to compress the fourth selector output, and that outputs a third compacted test result;
• a fifth selector that is connected to the third compactor and the part of the third input portion to selectively output the first compacted test result or the third compacted test result as a fifth selector output;
• and
• a third output portion that is connected to the fifth selector, and that outputs the fifth selector output to the external output portion as the compacted test result.