Program memory test access collar
AssigneeCypress Semiconductor Corporation
InventorsGregory J. Mann, Robert S. Hoffman
Life of this patent
Estimating the term…
Abstract
A memory access device includes logic to switch data from a processor memory bus to a memory bus in a first operational mode, and to switch data from a test bus to the memory bus in a second operational mode, and logic to switch address signals from the processor memory bus to the memory bus in the first operational mode. In the second operational mode the device accepts from the test bus a starting memory address for memory reads and writes, and automatically and independently of the test bus adjusts a memory address for reads and writes during burst memory operations.
Claims19
A memory access device comprising:
- hardware logic and/or logic embodied in machine memory circuits to switch data from a processor memory bus to a memory bus in a first operational mode, and to switch data from a test bus to the memory bus in a second operational mode;
- and
- hardware logic and/or logic embodied in machine memory circuits to switch address signals from the processor memory bus to the memory bus in the first operational mode, and in the second operational mode to accept from the test bus a starting memory address for memory reads and writes, and in the second operational mode to automatically adjust a memory address for reads and writes during burst memory operations wherein the test bus is not used in the propagation of signals to adjust the memory address for reads and writes during burst memory operations.
A device, comprising:
- a processor comprising a processor memory bus;
- a test bus;
- a memory accessed via a memory bus;
- and a memory access device to selectively enable access to a memory bus from either the processor memory bus or a test bus, comprising:
- logic to switch data from the processor memory bus to the memory bus in a first operational mode, and to switch data from the test bus to the memory bus in a second operational mode;
- and
- logic to switch address signals from the processor memory bus to the memory bus in the first operational mode, and in the second operational mode to accept from the test bus a starting memory address for memory reads and writes, and in the second operational mode to automatically adjust a memory address for reads and writes during burst memory operations wherein the test bus is not used in the propagation of signals to adjust the memory address for reads and writes during burst memory operations.
A method of selectively providing access to a memory from both a processor memory bus and a test bus, comprising:
- switching data from the processor memory bus to a memory bus in a first operational mode, and switching data from the test bus to the memory bus in a second operational mode;
- and
- switching address signals from the processor memory bus to the memory bus in the first operational mode, and, in the second operational mode, 1) accepting from the test bus a starting memory address for memory reads and writes, and 2) automatically adjusting a memory address for reads and writes during burst memory operations wherein the test bus is not used in the propagation of signals to adjust the memory address for reads and writes during burst memory operations.
Dependencies are inferred from the claim text.