Memory controller and signal synchronizing method thereof
AssigneeRealtek Semiconductor Corp.
InventorsYi Lin Chen, Yi Chih Huang
Life of this patent
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Abstract
A memory controller includes an output buffer for receiving a clock signal and outputting the clock signal to an external memory; and a replica buffer for receiving the clock signal and outputting the clock signal to a counting circuit; wherein the replica buffer and the output buffer have the same delay time such that the clock signal received by the counting circuit can be synchronized with that received by the external memory, and therefore the counting circuit can accurately count to a predetermined time according to the clock signal and output an enabling signal to enable a data control signal. The present invention further provides a signal synchronizing method for the memory controller.
Claims20
A memory controller for controlling a memory, comprising:
- a first buffer having an input for receiving a first clock signal and an output for outputting a second clock signal to the memory, wherein the second clock signal is delayed for a predetermined time with respect to the first clock signal;
- a second buffer having an input for receiving the first clock signal and an output for outputting a third clock signal, wherein the third clock signal is delayed for the predetermined time with respect to the first clock signal;
- and
- a counting circuit for receiving the third clock signal and counting to a predetermined value according to the third clock signal so as to output a control signal.
A memory controller, comprising:
- a first driving circuit having an input for receiving a first clock signal and an output for outputting a second clock signal to a memory, wherein the second clock signal is delayed for a predetermined time with respect to the first clock signal;
- a second driving circuit having an input for receiving the first clock signal and an output for outputting a third clock signal, wherein the third clock signal is delayed for the predetermined time with respect to the first clock signal;
- and
- a counting circuit for receiving the third clock signal and counting to a predetermined value according to the third clock signal so as to output a control signal.
A signal synchronizing method for controlling the signal output of a memory, the method comprising:
- receiving a first clock signal and outputting a second clock signal to the memory according to the first clock signal, wherein the second clock signal is delayed for a predetermined time with respect to the first clock signal;
- receiving the first clock signal and outputting a third clock signal according to the first clock signal, wherein the third clock signal is delayed for the predetermined time with respect to the first signal;
- and
- receiving the third clock signal and counting to a predetermined value according to the third clock signal so as to output a control signal.
Dependencies are inferred from the claim text.