Dynamic power management in an execution unit using pipeline wave flow control
AssigneeInternational Business Machines Corporation
InventorsChristopher Michael Abernathy, Gilles Gervais, Rolf Hilgendorf
Life of this patent
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Abstract
Power is conserved by dynamically applying clocks to execution units in a pipeline of a microprocessor. A clock to an execution unit is applied only when an instruction to the execution unit is valid. At other times when the execution unit needs not to be operational, the clock is not applied to the execution unit. In a preferred embodiment of the invention, a dynamiclock-control unit is used to provide a control signal to a local clock buffer providing a local clock to an execution unit.
Claims12
A microprocessor for dynamically reducing power consumption, the microprocessor comprising a main processor clock and being configured for executing at least an instruction, the microprocessor further comprising a computer executable program stored on a computer readable media, which when executed performs the steps of;
- storing operand data in a first stage of one or more storage components residing in the microprocessor, the first stage being clocked by at least a first clock derived from the main processor clock;
- transmitting the operand data from the first stage to a first combinatorial logic residing in the microprocessor, wherein the first clock is operational only during a first period of time when the operand data is processed by the first combinatorial logic;
- processing the operand data in the first combinatorial logic;
- generating first output data from the first combinatorial logic;
- storing the first output data in a second stage of one or more storage components residing in the microprocessor, the second stage being clocked by at least a second clock derived from the main processor clock;
- transmitting the first output data from the second stage to a second combinatorial logic residing in the microprocessor, wherein the second clock is operational only during a second period of time when the first output data is processed by the second combinatorial logic;
- processing the first output data in the second combinatorial logic;
- generating second output data from the second combinatorial logic;
- generating at least two instruction-valid control bits;
- in response to the instruction-valid control bits, reducing power consumption in the microprocessor by dynamically controlling the first and second clocks by selectively disabling at least one local clock buffer to prevent switching of the first clock or the second clock;
- generating a scan mode signal, wherein in response to the scan mode signal, the instruction-valid control bits enable the first clock and the second clock;
- and
- disabling the first clock by a first instruction-valid control bit in response to a first stop control signal and disabling the second clock by a second instruction-valid control bit in response to a second stop control signal.
A computer program product for dynamically reducing power consumption in a microprocessor configured for executing at least an instruction, the microprocessor having a main processor clock, the computer program product comprising a computer executable program stored on a non-transitory computer readable medium, the computer executable program comprising:
- computer program code for storing operand data in a first stage of one or more storage components residing in the microprocessor, the first stage being clocked by at least a first clock derived from the main processor clock;
- computer program code for transmitting the operand data from the first stage to a first combinatorial logic residing in the microprocessor, wherein the first clock is operational only during a first period of time when the operand data is processed by the first combinatorial logic;
- computer program code for processing the operand data in the first combinatorial logic;
- computer program code for generating first output data from the first combinatorial logic;
- computer program code for storing the first output data in a second stage of one or more storage components residing in the microprocessor, the second stage being clocked by at least a second clock derived from the main processor clock;
- computer program code for transmitting the first output data from the second stage to a second combinatorial logic residing in the microprocessor, wherein the second clock is operational only during a second period of time when the first output data is processed by the second combinatorial logic;
- computer program code for processing the first output data in the second combinatorial logic;
- computer program code for generating second output data from the second combinatorial logic;
- computer program code for generating at least two instruction-valid control bits;
- computer program code for, in response to the instruction-valid control bits, reducing power consumption in the microprocessor by dynamically controlling the first and second clocks by selectively disabling at least one local clock buffer to prevent switching of the first clock or the second clock;
- computer program code for generating a scan mode signal, wherein in response to the scan mode signal, the instruction-valid control bits enable the first clock and the second clock;
- and computer program code for disabling the first clock by a first instruction-valid control bit in response to a first stop control signal and disabling the second clock by a second instruction-valid control bit in response to a second stop control signal.
Dependencies are inferred from the claim text.