Method and logical apparatus for managing processing system resource use for speculative execution

A processor supporting concurrent execution of multiple hardware threads, said processor comprising:

• an instruction fetch unit for loading sequences of instructions for execution by said processor, wherein the sequences of instructions correspond to the multiple hardware threads;
• a branch processing unit for detecting when branch instructions are encountered, predicting a likely path of said branch instructions by a branch prediction unit, indicating to said instruction fetch unit a set of instructions to speculatively load for execution by said processor for the branches by the multiple threads prior to a condition of said branches being resolved, and upon resolution of branch conditions of the branches, updating indications of accuracy of the predicting performed by the branch prediction unit for the corresponding hardware threads;
• a control circuit coupled to said branch processing unit for determining that the indication of branch prediction accuracy corresponding to a given hardware thread indicates that one or more other hardware threads should be favored over the given hardware thread;
• and
• a thread control coupled to said control circuit for reducing execution resources supplied to said given thread in response to an indication from said control circuit that said control circuit has determined that the one or more hardware other threads should be favored over the given hardware thread, whereby said given hardware thread is throttled and instruction branches of said given hardware thread are resolved in an earlier phase of speculative execution.

A processor supporting concurrent execution of multiple hardware threads, said processor comprising:

• an instruction fetch unit for loading a sequence of instructions for execution by said processor;
• a branch processing unit for determining that a branch instruction has been encountered within a given hardware thread, determining a likely path of said branch and indicating to said instruction fetch unit an indicator of a set of instructions to speculatively load for execution by said processor prior to a condition of said branch being resolved;
• a control circuit coupled to said branch processing unit for detecting when an accuracy of said determining by said branch processing unit is below a predetermined threshold;
• and
• a thread control coupled to said control circuit for reducing execution resources supplied to said given thread in response to an indication from said control circuit that said control circuit has detected that said accuracy is below said predetermined threshold, wherein said thread control reduces a number of execution slices allocated to said given hardware thread in response to said indication from said control circuit.

A processor supporting concurrent execution of multiple hardware threads, said processor comprising:

• an instruction fetch unit for loading a sequence of instructions for execution by said processor;
• a branch processing unit for determining that a branch instruction has been encountered within a given hardware thread, determining a likely path of said branch and indicating to said instruction fetch unit an indicator of a set of instructions to speculatively load for execution by said processor prior to a condition of said branch being resolved;
• a control circuit coupled to said branch processing unit for detecting when an accuracy of said determining by said branch processing unit is below a predetermined threshold;
• a storage for storing prefetched instructions for said given hardware thread;
• and
• a thread control coupled to said control circuit for reducing execution resources supplied to said given hardware thread in response to an indication from said control circuit that said control circuit has detected that said accuracy is below said predetermined threshold, and wherein the size of the storage allocated to said given hardware thread is reduced by the thread control in response to said indication from said control circuit.