Mechanism for selecting instructions for execution in a multithreaded processor
AssigneeOpen Computing Trust I & II
InventorRobert T. Golla
Life of this patent
Estimating the term…
Abstract
In one embodiment, a multithreaded processor includes a plurality of buffers, each configured to store instructions corresponding to a respective thread. The multithreaded processor also includes a pick unit coupled to the plurality of buffers. The pick unit may pick from at least one of the buffers in a given cycle, a valid instruction based upon a thread selection algorithm. The pick unit may further cancel, in the given cycle, the picking of the valid instruction in response to receiving a cancel indication.
Claims40
A multithreaded processor, comprising:
- a plurality of buffers, each configured to store a plurality of instructions corresponding to a respective thread;
- and
- a pick unit coupled to the plurality of buffers and configured to pick from at least one of the plurality of buffers in a given cycle, a valid instruction based upon a thread selection algorithm;
- wherein the pick unit is further configured to cancel, in the given cycle, the picking of the valid instruction in response to receiving a cancel indication.
A method of selecting instructions with a multithreaded processor, said method comprising:
- storing a plurality of instructions corresponding to a respective thread within a plurality of respective buffers;
- picking from at least one of the plurality of buffers in a given cycle, a valid instruction based upon a thread selection algorithm;
- and
- canceling, in the given cycle, the picking of the valid instruction in response to receiving a cancel indication.
A system, comprising:
- a system memory;
- a multithreaded processor coupled to the system memory, wherein the multithreaded processor includes:
- a plurality of buffers, each configured to store a plurality of instructions corresponding to a respective thread;
- and
- a pick unit coupled to the plurality of buffers and configured to pick from at least one of the plurality of buffers in a given cycle, a valid instruction based upon a thread selection algorithm;
- wherein the pick unit is further configured to cancel, in the given cycle, the picking of the valid instruction in response to receiving a cancel indication.
A multithreaded processor, comprising:
- a plurality of buffers, each configured to store a plurality of instructions corresponding to a respective thread;
- a pick unit coupled to the plurality of buffers and configured to concurrently pick from one or more of the plurality of buffers in a given cycle, a valid instruction based upon a least recently picked selection algorithm;
- wherein the pick unit is further configured to cancel, in the given cycle, the picking of the valid instruction in response to receiving a cancel indication;
- and
- an execution pipeline coupled to the pick unit and configured to concurrently execute the valid instruction from each of the one or more of the plurality of buffers in a given cycle.
A method of selecting instructions with a multithreaded processor, said method comprising:
- storing a plurality of instructions corresponding to a respective thread within a plurality of respective buffers;
- concurrently picking from one or more of the plurality of buffers in a given cycle, a valid instruction based upon a least recently picked selection algorithm;
- canceling, in the given cycle, the picking of the valid instruction in response to receiving a cancel indication;
- and
- concurrently executing the valid instruction from each of the one or more of the plurality of buffers in a given cycle.
Dependencies are inferred from the claim text.