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US 7,890,732 B2Granted
Memory card and semiconductor device
AssigneeKabushiki Kaisha Toshiba
InventorHiroshi Sukegawa
Life of this patent
Estimating the term…
Abstract
A memory card includes a controller and a nonvolatile semiconductor memory. The controller manages a correspondence between a first address in a semiconductor memory of a first erase block size and a second address in a semiconductor memory of a second erase block size other than the first erase block size. The nonvolatile semiconductor memory is a memory of the second erase block size. The controller executes access to the nonvolatile semiconductor memory by the second address.
Claims27
A memory system comprising:
- a nonvolatile semiconductor memory which includes a plurality of blocks each having a plurality of pages, in which data is erasable in units of blocks, an erase block size of the nonvolatile semiconductor memory being larger than an erase block size of a memory assumed by a host device;
- eight input/output terminals to input/output a command, an address, and data from/to an outside of the memory system;
- and
- a ready/busy terminal to inform the outside of the memory system of an internal state of the memory system,
- the memory system being configured to perform processing of:
- in one write operation, capturing a first command, an address, and data, with 8-bit width via the eight input/output terminals,
- managing a first table for converting a first physical address of the memory assumed by the host device into a first logical address of the memory assumed by the host device, and a second table for converting the first logical address into a second physical address of the nonvolatile semiconductor memory, the first table and the second table being provided in a RAM,
- converting the first physical address into the second physical address using the first table and the second table when accessing the nonvolatile semiconductor memory, and
- writing the data to the nonvolatile semiconductor memory while assuring that a plurality of data items, which are captured via the eight input/output terminals by a plurality of write operations, are stored in one page, and
- the memory system being further configured to perform processing of:
- upon receiving an erase command from the host device, notifying the host device that data corresponding to the erase command has been erased, while not actually erasing the data corresponding to the erase command.
8 more elements
A memory system comprising:
- a nonvolatile semiconductor memory which includes a plurality of blocks each having a plurality of pages, in which data is erasable in units of blocks, an erase block size of the nonvolatile semiconductor memory being larger than an erase block size of a memory assumed by a host device;
- M input/output terminals (M is a natural number larger than 1) to input/output a command, an address, and data from/to an outside of the memory system;
- and
- a ready/busy terminal to inform the outside of the memory system of an internal state of the memory system,
- the memory system being configured to perform processing of:
- in one write operation, capturing a command, an address, and data, with M-bit width via the M input/output terminals,
- managing a first table for converting a first physical address of the memory assumed by the host device into a first logical address of the memory assumed by the host device, and a second table for converting the first logical address into a second physical address of the nonvolatile semiconductor memory, the first table and the second table being provided in a RAM,
- converting the first physical address into the second physical address using the first table and the second table when accessing the nonvolatile semiconductor memory, and
- writing the data to the nonvolatile semiconductor memory while assuring that a plurality of data items, which are captured via the M input/output terminals by a plurality of write operations, are stored in one page, and
- the memory system being further configured to perform processing of:
- upon receiving an erase command from the host device, notifying the host device that data corresponding to the erase command has been erased, while not actually erasing the data corresponding to the erase command.
8 more elements
A memory system comprising:
- a nonvolatile semiconductor memory which includes a plurality of blocks each having a plurality of pages, in which data is erasable in units of blocks, an erase block size of the nonvolatile semiconductor memory being larger than an erase block size of a memory assumed by a host device;
- M input/output terminals (M is a natural number larger than 1) to input/output a command, an address, and data from/to an outside of the memory system;
- and
- a ready/busy terminal to inform the outside of the memory system of an internal state of the memory system,
- the memory system being configured to perform processing of:
- in one write operation, capturing a command, an address, and data, with M-bit width via the M input/output terminals,
- managing a first table for converting a first physical address of the memory assumed by the host device into a first logical address of the memory assumed by the host device, and a second table for converting the first logical address into a second physical address of the nonvolatile semiconductor memory, the first table and the second table being provided in a RAM,
- converting the first physical address into the second physical address using the first table and the second table when accessing the nonvolatile semiconductor memory, and
- data size of one page of the nonvolatile semiconductor memory being two or more times as large as a maximum size of data that is captured by the one write operation of the memory system, and
- the memory system being further configured to perform processing of:
- upon receiving an erase command from the host device, notifying the host device that data corresponding to the erase command has been erased, while not actually erasing the data corresponding to the erase command.
8 more elements
Dependencies are inferred from the claim text.