Prioritization of out-of-order data transfers on shared data bus

#The invention relates to computers and data processing systems, and in particular to scheduling data transfers on a shared data bus.

#Computer technology continues to advance at a remarkable pace, with numerous improvements being made to the performance of both processors—the “brains” of a computer—and the memory that stores the information processed by a computer. In general, a processor operates by executing a sequence of instructions that form a computer program. The instructions are typically stored in a memory system having a plurality of storage locations identified by unique memory addresses. The memory addresses collectively define a “memory address space,” representing the addressable range of memory addresses that can be accessed by a processor.

#A number of computer designs utilize multiple processors operating in parallel with one another to increase overall computing performance. In a symmetric multiprocessing (SMP) environment, for example, multiple processors share at least a portion of the same memory system to permit the processors to work together to perform more complex tasks. The multiple processors are typically coupled to one another and to the shared memory by a shared bus, often referred to as a system or processor bus, or other like interconnection network.

#FIG. 1 is a functional block diagram illustrating the scheduling of data transfers on a data bus in a manner consistent with the invention.

#FIG. 2 is a block diagram an exemplary implementation of a computer incorporating a split transaction processor bus and data bus scheduler consistent with the invention.

#FIG. 3 is a block diagram of one exemplary implementation of the data bus scheduler of FIG. 2.

#The embodiments discussed and illustrated hereinafter utilize data bus scheduling logic that provides uncontested priority to out-of-order data transfers over in-order data transfers awaiting communication over a data bus. In an exemplary embodiment of the invention, uncontested priority refers to an algorithm where a pending out-of-order data transfer, i.e., an out-of-order data transfer that is ready to be transmitted over the data bus, is always granted access to the data bus irrespective of whether any in-order data transfer is currently pending. Moreover, uncontested priority in such an algorithm results in pending in-order data transfer being granted access to the data bus only if no out-of-order data transfer is currently pending.

#An in-order data transfer within the context of the invention refers to a data transfer that is ready to be transferred over the data bus immediately after its associated operation has been initiated. In an exemplary embodiment of the invention where a shared bus incorporates split transactions and a data bus that is separate from the bus over which address and command information is communicated, an in-order data transfer is a data transfer that is ready to be initiated once the associated command is communicated over the separate bus. While other types of data transfers may be considered in-order data transfers consistent with the invention, two such types of data transfers include write or cast out data transfers, typically initiated to write back or cast out a modified cache line to memory, and cache-to-cache or intervention data transfers, typically initiated to reply to read requests directed to locally cached cache lines. In this regard, cache-to-cache or intervention data transfers may also be considered to be forms of in-order read data responses, given they are initiated in response to a read request.

#An out-of-order data transfer within the context of the invention refers to a data transfer that is “out of order” with respect to the transaction traffic on a shared bus, and is typically ready to be transferred some time after its associated operation has been initiated. In the aforementioned exemplary embodiment, an out-of-order data transfer is typically a deferred read data transfer initiated in response to receiving requested data from main memory that was originally requested by a deferred read request.