Delegated write for race avoidance in a processor

A synchronization unit with race avoidance capability in a system including multiple-slice, redundant loosely-coupled processors and memory, the synchronization unit comprising:

• a logical gateway that performs voted-write operations as a delegate for the processors which mutually compares data from the processors and resolves data discrepancies in write data among the processors in favor of a majority of the processors that agree and receives data and memory address information from the processors and writes resolved data to addressed memory as a delegate for the processors;
• a race delegation sequence number register;
• and
• a race delegation data register;
• a logic that sets race delegation sequence, data, and address, and monitors completion of a delegated write;
• a processor-executable logic that maintains an internal delegated write sequence number and increments the internal delegated write sequence number with each enqueued delegated write operation;
• and
• a delegate-executable logic that increments a count with each performed delegated write, the count being reflected to a host memory at a defined address.

A method of avoiding a race condition comprising:

• receiving checked-writes from a multiple-slice, redundant loosely-coupled processor, the checked writes specifying a data value and a target memory address;
• mutually comparing data from a plurality of processors in a voted-write operation;
• resolving data discrepancies in write data among the plurality of processors in favor of a majority of the processors that agree in the checked-write;
• upon completion of the checked-writes, writing the resolved data value by delegation to the address targeted in at least one memory;
• setting a data register with the specified data value;
• setting an address register with the specified target memory address;
• upon completion of the checked-writes, writing the data register value to the address register specified address
• receiving an update from a plurality of processor slices at different times with respect to an input/output (I/O) operation;
• and
• writing the update to the at least one memory with delegation into a Direct Memory Access (DMA) transaction stream at a time consistent for all processor slices whereby order of all writes to each memory is identical.

A method of avoiding a race condition comprising:

• receiving checked-writes from a multiple-slice, redundant loosely-coupled processor, the checked writes specifying a data value and a target memory address;
• mutually comparing data from a plurality of processors in a voted-write operation;
• resolving data discrepancies in write data among the plurality of processors in favor of a majority of the processors that agree in the checked-write;
• upon completion of the checked-writes, writing the resolved data value by delegation to the address targeted in at least one memory;
• initializing a race delegation sequence number register prior to delegated write initiation;
• and
• monitoring the race delegation sequence number register to determine whether delegation resources are available or currently in usage.

A computer system comprising:

• at least one processor slice executable in combination as a redundant loosely-coupled processor and including a memory;
• a logical synchronization unit coupled to the at least one processor slice, the logical synchronization unit asynchronously receiving data and address information from multiple processor slices, performing voted-write operations as a delegate for the processor slices which mutually compare data from the processor slices and resolve data discrepancies in write data among the processor slices in favor of a majority of the processors that agree, and writing the resolved data by delegation to an address information-specified address in the memory of multiple processor slices synchronously among the multiple processor slices;
• and
• a logic in the at least one processor slice that checks a delegate write sequence number to determine whether additional delegated write engines are available or currently in use.