Cache injection using semi-synchronous memory copy operation

A system for inserting data into a cache memory based on information in a semi-synchronous memory copy instruction, the system comprising:

• a processor with at least cache injection register coupled thereto;
• a main memory communicatively coupled to the processor;
• a cache memory communicatively coupled to the processor;
• an opcode, which is interpreted by the processor, for a semi-synchronous memory copy operation associated with a section of the main memory, wherein the semi-synchronous memory copy operation operates semi-synchronously with a superscalar processor to provide maximum processor utilization such that the superscalar processor is able to execute at least one additional instruction on another section of the main memory during the semi-synchronous memory copy operation, and wherein the semi-synchronous memory copy operation takes virtual addresses as arguments to provide non-pinning of virtual memory pages that tolerate page faults referenced by the virtual addresses;
• a memory copy unit communicatively coupled to the processor and the cache memory for
• checking the semi-synchronous memory copy operation for a given value in at least one cache injection bit, wherein the cache injection bit is associated with a given value indicating a given number of lines of destination data to be transferred;
• and
• copying, based on the cache injection bit, a predefined number of lines of destination data into at least one level of cache memory
• wherein the processor executes at least one subsequent instruction on the memory and copies a remaining set of destination data to a target location within the memory during the copying of the predefined number of lines of destination data into the at least one level of cache memory.

A computer program product for inserting data into a cache memory based on information in a semi-synchronous memory copy instruction, the computer program product on an information processing system comprising:

• a computer readable storage medium readable by the information processing system, the computer readable storage medium instructions for performing:
• determining a start of a semi-synchronous memory copy operation associated with a section of a single memory, wherein the semi-synchronous memory copy operation operates semi-synchronously with a superscalar processor to provide maximum processor utilization such that the superscalar processor is able to execute at least one additional instruction on another section of the single memory during the semi-synchronous memory copy operation, and wherein the semi-synchronous memory copy operation takes virtual addresses as arguments to provide non-pinning of virtual memory pages that tolerate page faults referenced by the virtual addresses;
• checking the semi-synchronous memory copy operation for a given value in at least one cache injection bit, wherein the cache injection bit is associated with a given value indicating a given number of lines of destination data to be transferred;
• copying, based on the cache injection bit, a predefined number of lines of destination data into at least one level of cache memory;
• and
• executing at least one subsequent instruction on the memory and copying a remaining set of destination data to a target location within the memory during the copying of the predefined number of lines of destination data into the at least one level of cache memory.