Processing unit incorporating L1 cache bypass
AssigneeInternational Business Machines Corporation
InventorsMiguel Comparan, Eric Oliver Mejdrich, Adam James Muff
Life of this patent
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Abstract
A circuit arrangement and method bypass the storage of requested data in a higher level cache of a multi-level memory architecture during the return of the requested data to a requester, while caching the requested data in a lower level cache. For certain types of data, e.g., data that is only used once and/or that is rarely modified or written back to memory, bypassing storage in a higher level cache reduces the likelihood of the requested data casting out frequently used data from the higher level cache. By caching the data in a lower level cache, however, the lower level cache can still snoop data requests and return requested data in the event the data is already cached in the lower level cache.
Claims24
A circuit arrangement, comprising:
- a single instruction multiple data (SIMD) execution unit including an SIMD register file;
- a fixed point execution unit including a general purpose register file;
- a memory bus configured to be coupled to a memory;
- an L1 cache;
- an L2 cache;
- and
- control logic coupled to the SIMD and fixed point execution units, the memory bus and the L1 and L2 caches, the control logic configured to:
- in response to each request from the fixed point execution unit for first data, issue the request from the fixed point execution unit on the memory bus to initiate retrieval of the first data from the memory, and upon return of the first data over the memory bus, initiate storage of the first data in the general purpose register file and the L1 cache;
- and
- in response to each request from the SIMD execution unit for second data, issue the request from the SIMD execution unit on the memory bus to initiate retrieval of the second data from the memory, and upon return of the second data over the memory bus, initiate storage of the second data in the SIMD register file while bypassing the L1 cache;
- and
- wherein the L2 cache is configured to snoop the memory bus and store in the L2 cache any data requested by the control logic over the memory bus such that, in response to each request from the fixed point execution unit, the first data is stored in the fixed point execution unit, the L1 cache and the L2 cache, and in response to each request from the SIMD execution unit, the second data is stored in the SIMD execution unit and the L2 cache, but not in the L1 cache.
A circuit arrangement, comprising:
- a requester configured to generate a first request for data from a multi-level memory architecture;
- first and second caches disposed in the multi-level memory architecture,
- the first cache disposed at a higher level in the multi-level memory architecture than the second cache;
- and
- control logic coupled to the first and second caches, the control logic configured to, in response to the first request, retrieve the requested data from the multi-level memory architecture, cause the requested data to be cached in the second cache, forward the requested data to the requester, and bypass caching of the requested data in the first cache, wherein the control logic is configured to, in response to a second request for second data, retrieve the second data from the multi-level memory architecture, cause the second data to be cached in the second cache, cause the second data to be cached in the first cache, and forward the second data to the requester, and wherein the control logic is configured to selectively operate in a bypass mode responsive to software control to selectively enable or disable caching of the second data in the first cache.
A method of retrieving data from a multi-level memory architecture of the type including first and second caches disposed in the multi-level memory architecture, with the first cache disposed at a higher level in the multi-level memory architecture than the second cache, the method comprising, in response from a request for data from a requestor:
- retrieving the requested data from the multi-level memory architecture;
- causing the requested data to be cached in the second cache;
- forwarding the requested data to the requester;
- and
- bypassing caching of the requested data in the first cache;
- wherein the request for data is a first request for first data, the method further comprising, in response to a second request for second data:
- retrieving the second data from the multi-level memory architecture;
- causing the second data to be cached in the second cache;
- causing the second data to be cached in the first cache;
- and
- forwarding the second data to the requester;
- and wherein the method further comprises selecting a bypass mode responsive to software control to selectively disable caching of the second data in the first cache.
Dependencies are inferred from the claim text.