Memory systems for automated computing machinery

A memory system comprising:

• a memory controller;
• an outbound link, the memory controller connected to the outbound link, the outbound link comprising a number of conductive pathways that conduct memory signals from the memory controller to memory buffer devices in a first memory layer;
• at least two memory buffer devices in a first memory layer, each memory buffer device in the first memory layer connected to the outbound link to receive memory signals from the memory controller;
• additional outbound links, each additional outbound link comprising a number of conductive pathways connected to a memory buffer device of the first memory layer so as to conduct memory signals from a memory buffer device in the first memory layer to two or more additional memory buffer devices in an additional memory layer, each additional outbound link comprising a number of conductive pathways smaller than the number of conductive pathways in the outbound link connecting the memory controller to the memory buffer devices in the first memory layer;
• and
• at least two additional memory buffer devices in an additional memory layer, each additional memory buffer device connected to at least two of the additional outbound links so as to receive all memory signals transmitted from the memory controller on the outbound link between the memory controller and the memory buffer devices in the first memory layer.

A memory system comprising:

• a memory controller;
• an outbound link, the memory controller connected to the outbound link, the outbound link comprising a number of conductive pathways that conduct memory signals from the memory controller to memory buffer devices in a first memory layer;
• at least two memory buffer devices in a first memory layer, each memory buffer device in the first memory layer connected to the outbound link to receive memory signals from the memory controller;
• a plurality of separate inbound links, one inbound link connected from each memory buffer device in the first memory layer to the memory controller for transmission of memory signals from each memory buffer device in the first memory layer to the memory controller;
• additional inbound links, each additional inbound link comprising a number of conductive pathways connected to a memory buffer device of the first memory layer so as to conduct to the memory buffer device of the first memory layer memory signals from an additional memory buffer device of an additional memory layer, each additional inbound link comprising a number of conductive pathways that is equal to the number of conductive pathways in the inbound links connecting the memory controller to the memory buffer devices in the first memory layer;
• and
• at least two additional memory buffer devices in an additional memory layer, each additional memory buffer device connected to one of the additional inbound links so as to send from the additional memory buffer device to one of the memory buffer devices of the first level of memory all memory signals to be transmitted to the memory controller from each memory buffer device of the first memory layer.

A memory system comprising:

• a memory controller;
• an outbound link, the memory controller connected to the outbound link, the outbound link comprising a number of conductive pathways that conduct memory signals from the memory controller to memory buffer devices in a first memory layer;
• at least two memory buffer devices in a first memory layer, each memory buffer device in the first memory layer connected to the outbound link to receive memory signals from the memory controller;
• an additional outbound link, the additional outbound link comprising a number of conductive pathways connected to a first memory buffer devices in the first memory layer so as to conduct all outbound memory signals from the first memory buffer device in the first memory layer to at least two additional memory buffer devices in an additional memory layer, the additional outbound link comprising a number of conductive pathways that is equal to the number of conductive pathways in the outbound link connecting the memory controller to the memory buffer devices in the first memory layer;
• and
• at least two additional memory buffer devices in an additional memory layer, each additional memory buffer device connected to the additional outbound link so as to receive through the additional outbound link and through the first memory buffer device in the first memory layer all outbound memory signals from the memory controller,
• wherein at least one memory buffer device in the first memory layer is connected through no additional outbound link to any additional memory buffer device of the additional memory layer.

A memory system comprising:

• a memory controller;
• an outbound link, the memory controller connected to the outbound link, the outbound link comprising a number of conductive pathways that conduct memory signals from the memory controller to memory buffer devices in a first memory layer;
• at least two memory buffer devices in a first memory layer, each memory buffer device in the first memory layer connected to the outbound link to receive memory signals from the memory controller;
• wherein
• the memory is sliced so that each memory buffer device in a layer of memory administers only a portion of the memory addressed by an outbound memory signal from the memory controller, and the memory system further comprises:
• an inbound link, the inbound link comprising two or more partial inbound links, each partial inbound link connected from a memory buffer device of the first memory layer to the memory controller for transmission of inbound memory signals from each memory buffer device in the first memory layer to the memory controller, each partial inbound link comprising a portion of the conductive pathways of the inbound link, each partial inbound link carrying inbound memory signals representing the contents of a portion of the memory addressed by an outbound read memory signal from the memory controller.

A memory system comprising:

• a memory controller;
• an outbound link, the memory controller connected to the outbound link, the outbound link comprising a number of conductive pathways that conduct memory signals from the memory controller to memory buffer devices in a first memory layer;
• at least two memory buffer devices in a first memory layer, each memory buffer device in the first memory layer connected to the outbound link to receive memory signals from the memory controller;
• a first additional outbound link, the first additional outbound link connected to a first memory buffer device of the first memory layer so as to conduct memory signals received from the memory controller through the first memory buffer device of the first memory layer to at least two additional memory buffer devices in an additional memory layer, the first additional outbound link initially enabled;
• a second additional outbound link, the second additional outbound link connected to a second memory buffer device of the first memory layer so as to conduct memory signals received from the memory controller through the second memory buffer device of the first memory layer to the at least two additional memory buffer devices in the additional memory layer, the second additional outbound link initially disabled;
• and
• the at least two additional memory buffer devices in the additional memory layer, each additional memory buffer device connected to the first additional outbound link and the second additional outbound link so as to receive memory signals from the memory controller through either the first additional outbound link or the second additional outbound link.

A memory system comprising:

• a memory controller;
• an outbound link, the memory controller connected to the outbound link, the outbound link comprising a number of conductive pathways that conduct memory signals from the memory controller to memory buffer devices in a first memory layer;
• at least two memory buffer devices in a first memory layer, each memory buffer device in the first memory layer connected to the outbound link to receive memory signals from the memory controller;
• a first inbound link, the first inbound link connected from a first memory buffer device in the first memory layer to the memory controller so as to communicate inbound memory signals from the first memory buffer device to the memory controller;
• and
• a second inbound link, the second inbound link connected from a second memory buffer device in the first memory layer to the first memory buffer device in the first memory layer so as to communicate inbound memory signals from the second memory buffer device to the first memory buffer device and through the first memory buffer device and the first inbound link to the memory controller.