Method for modeling performance of embedded processors having combined cache and memory hierarchy
AssigneeSeagate Technology LLC
InventorDavid C. Cressman
Life of this patent
Estimating the term…
Abstract
A method allocating firmware objects between different types of memory in a product model based on a frequency of access of each firmware object in trace data. The allocated firmware objects and trace data are used to simulate the performance of the product model. Memory access statistics obtained during the simulation may be used to analyze product model performance in the frequency and time domains.
Claims27
A method comprising:
- determining access frequencies of firmware objects;
- ranking the firmware objects based on the access frequency of each firmware object;
- and
- allocating the firmware objects between a high-speed on-chip memory and a cache coupled to an external memory based on the ranking of the firmware objects.
A method comprising:
- analyzing trace data to obtain information regarding firmware objects;
- ranking the firmware objects based on the trace data;
- and
- allocating the firmware objects to a high-speed on-chip memory and a cache coupled to an external memory based on ranking.
One or more computer readable storage media storing computer executable instructions for executing a computer process for allocating firmware objects to memory, the computer process comprising:
- analyzing trace data to obtain information regarding firmware objects;
- ranking the firmware objects based on the trace data;
- and
- allocating the firmware objects to a high-speed on-chip memory and a cache coupled to an external memory based on ranking.
Dependencies are inferred from the claim text.