Timing functions to optimize code-execution time
AssigneeAnadigics, Inc.
InventorMichael Joseph Raneri
Life of this patent
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Abstract
A method and system for optimizing a test plan of an Integrated Circuit (IC). The test plan includes two or more test sequences. A test sequence includes the measurement of a parameter of the IC. The total test time of the IC is reduced by performing one or more activities during a desired wait time associated with the measurement of the parameter. The test plan may be further optimized by modifying the one or more activities performed during the desired wait time.
Claims8
A method for executing a test sequence for testing an integrated circuit, the test sequence comprising measurement of at least one parameter of the integrated circuit, the method comprising:
- a) initializing the measurement of the at least one parameter, the measurement having a desired wait time;
- b) performing one or more activities during the desired wait time;
- c) performing the measurement of the at least one parameter at the end of the desired wait time;
- and
- d) modifying the test sequence based on at least one of the desired wait time, and the difference between the desired wait time and the time elapsed in performing the one or more activities.
Dependencies are inferred from the claim text.