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US 7,890,286 B2Granted
Test circuit for performing multiple test modes
AssigneeHynix Semiconductor Inc.
InventorYoung-Do Hur
Life of this patent
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AssigneeHynix Semiconductor Inc.
InventorYoung-Do Hur
Estimating the term…
A test circuit includes a first reset pulse generator configured to generate a first reset pulse when a test mode is performed or when power is up, a test mode maintenance signal generator configured to provide a test mode maintenance signal activated in response to a predetermined consecutive test information data, the activation of the test mode maintenance signal being controlled by the first reset pulse, a second reset pulse generator configured to generate a second reset pulse when the test information data is received as a predetermined test mode reset data or when power is up, and a test mode selection signal generator configured to receive the test information data provided from the test mode maintenance signal generator and the test mode maintenance signal and to generate a specific test mode selection signal, the activation of the specific test mode selection signal being controlled by the second reset pulse.
A test circuit comprising:
A test circuit for performing multiple test modes, comprising:
Dependencies are inferred from the claim text.