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US 7,889,951 B2Granted
Processor to processor communication in a data driven architecture
AssigneeIntel Corporation
InventorLouis A. Lippincott
Life of this patent
Estimating the term…
Abstract
In an embodiment, an apparatus includes a first processor that includes a first processor element. The apparatus also includes a second processor that includes a second processor element. The first processor is configured to transmit data to the second processor through a third processor, wherein no processor element within the third processor is configured to perform a process operation on the data as part of the transmission of the data from the first processor to the second processor.
Claims19
An apparatus comprising:
- a first processor that includes a first processor element;
- and
- a second processor that includes a second processor element, wherein the first processor is configured to transmit data to the second processor through a third processor, wherein no processor element within the third processor is configured to perform a process operation on the data as part of the transmission of the data from the first processor to the second processor, wherein the first processor includes a type of hardware accelerator that is not included in the second processor.
An apparatus comprising:
- a first processor that includes a first processor element that is configured to perform a first data process operation;
- and
- a second processor that includes a second processor element that is configured to perform a second data process operation based on an output from the first data process operation, the first processor to transmit the output from the first data process operation to the second processor based on a logical connection that includes traversal through a port ring of a third processor, wherein a third processor element within the third processor is not configured to perform a data process operation between the first data process operation and the second data process operation, wherein the first processor includes a type of hardware accelerator that is not included in the second processor and wherein the first processor element in the first processor is configured to perform the first data process operation on data streams received into the expansion interface at least simultaneously in part with second data process operation performed by the second processor element in the second processor.
A method comprising:
- receiving a stream of data in a first processor having a first processor element;
- performing, by the first processor element, image processing operations on at least a part of the stream of data;
- and
- transmitting a result of the image processing operations to a second processor through a third processor having a third processor element, independent of image processing operations by the third processor element, wherein the first processor includes a type of hardware accelerator that is not included in the second processor.
1 more element
A method comprising:
- performing, by a hardware accelerator in a first image signal processor within a multi-processor point-to-point configuration, the following operations until receipt of image data from an image scanning operation is complete,
- executing, by a first processor element in the first image signal processor, an image process operation on the image data;
- and
- transmitting a result of the image process operation to a second image signal processor within the multi-processor point-to-point configuration through a logical connection that includes a number of ports of a number of other different image signal processors within the multi-processor point-to-point configuration, wherein a type of the hardware accelerator is not included in at least one of the number of other different image signal processors.
1 more element
A non-transitory computer readable medium that provides instructions, which when executed by a computer, cause said computer to perform operations comprising:
- receiving a stream of data in a first processor having a first processor element;
- performing, by the first processor element, image processing operations on at least a part of the stream of data;
- and
- transmitting a result of the image processing operations to a second processor through a third processor having a third processor element, independent of image processing operations by the third processor element, wherein the first processor includes a type of hardware accelerator that is not included in the second processor.
1 more element
A non-transitory computer readable storage medium that provides instructions, which when executed by a computer, cause said computer to perform operations comprising:
- recursively performing, by a hardware accelerator in a first image signal processor within a multi-processor point-to-point configuration, the following operations until receipt of image data from an image scanning operation is complete,
- executing, by a first processor element in the first image signal processor, an image process operation on the image data;
- and
- transmitting a result of the image process operation to a second image signal processor within the multi-processor point-to-point configuration through a logical connection that includes a number of ports of a number of other different image signal processors within the multiprocessor point-to-point configuration, wherein a type of the hardware accelerator is not included in at least one of the number of other different image signal processors.
1 more element
Dependencies are inferred from the claim text.