US 7,889,832 B2 · Bootstrap circuit, shift register employing the same and display device · patentgrep

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Abstract

Disclosed is a shift register which includes first transistor connected between a first clock signal terminal and an output terminal, a second transistor with a gate connected to an input terminal and a source connected to a gate of the first transistor, a third transistor with a gate connected to a second clock signal terminal, an inverter with an input connected to the input terminal, a fourth transistor cascode connected to the third transistor with a gate connected to an output of the inverter, a fifth transistor connected between the gate of the first transistor and a power supply terminal, a sixth transistor connected between the fourth transistor and the power supply terminal with a gate connected to the input terminal, and a seventh transistor connected between the output terminal and the power supply terminal, the fifth and seventh transistors having gates connected in common to a connection node of the fourth and the sixth transistors.

Claims19

Dependent claims

A bootstrap circuit which receives an input signal and a plurality of clock signals and generates an output signal, comprising:

a first transistor that receives a first clock signal and that, when in a conductive state, outputs the first clock signal as the output signal;
a first control unit that is connected to a control terminal of the first transistor and that renders the first transistor conductive, in response to the input signal;
a second control unit that is connected to the control terminal of the first transistor and that renders the first transistor non-conductive in response to an input signal and to a second clock signal, the second clock signal having a phase lead by a half cycle or by one phase with respect to the first clock signal, with the plurality of clock signals constituting N-phase clocks, where N is an integer greater than or equal to two;
and
a third control unit that is connected to the control terminal of the first transistor and that renders the first transistor non-conductive, in response to a control signal, the control signal being different from the input signal.

2 more elements

A bootstrap circuit which receives an input signal and a plurality of clock signals and generates an output signal, comprising:

a first transistor that receives a first clock signal and that, when in a conductive state, outputs the first clock signal as the output signal;
a first control unit that is connected to a control terminal of the first transistor and that renders the first transistor conductive, in response to the input signal;
and
a second control unit that is connected to the control terminal of the first transistor and that renders the first transistor non-conductive in response to an input signal and to a second clock signal, the second clock signal having a phase lead by a half cycle or by one phase with respect to the first clock signal, with the plurality of clock signals constituting N-phase clocks, where N is an integer greater than or equal to two,
wherein the second control unit comprises:
a third transistor that has conducting and non-conducting states thereof controlled by the second clock signal;
a fourth transistor that is connected in series with the third transistor;
an inverter circuit that controls conducting and non-conducting states of the fourth transistor;
a fifth transistor that supplies to a control terminal of the first transistor a potential that renders the first transistor non-conductive;
and
a sixth transistor that is connected between a control terminal of the fifth transistor and a power supply terminal and that renders the fifth transistor non-conductive.

8 more elements

A bootstrap circuit which receives an input signal and a plurality of clock signals and generates an output signal, comprising:

a first transistor that receives a first clock signal and that, when in a conductive state, outputs the first clock signal as the output signal;
a first control unit that is connected to a control terminal of the first transistor and that renders the first transistor conductive, in response to the input signal;
and
a second control unit that is connected to the control terminal of the first transistor and that renders the first transistor non-conductive in response to an input signal and to a second clock signal, the second clock signal having a phase lead by a half cycle or by one phase with respect to the first clock signal, with the plurality of clock signals constituting N-phase clocks, where N is an integer greater than or equal to two,
wherein the first transistor is connected between a first clock signal terminal at which the first clock signal is received and an output terminal at which the output signal is output,
the first control unit includes a second transistor that has a control terminal connected to an input terminal at which the input signal is received and that has one terminal connected to a control terminal of the first transistor;
and
the second control unit includes:
a third transistor that has a control terminal connected to a second clock signal terminal at which the second clock signal is received;
an inverter circuit that has an input connected to the input terminal;
a fourth transistor that is cascode connected to the third transistor and that has a control terminal connected to an output of the inverter circuit;
a fifth transistor that is connected between the control terminal of the first transistor and a power supply terminal;
a sixth transistor that is connected between the fourth transistor and the power supply terminal and that has a control terminal connected to the input terminal;
and
a seventh transistor that is connected between the output terminal and the power supply terminal,
the fifth and seventh transistors having control terminals connected in common to a connection node of the fourth transistor and the sixth transistor.

13 more elements

A bootstrap circuit which receives an input signal and a plurality of clock signals and generates an output signal, comprising:

a first transistor that receives a first clock signal and that, when in a conductive state, outputs the first clock signal as the output signal;
a first control unit that is connected to a control terminal of the first transistor and that renders the first transistor conductive, in response to the input signal;
and
a second control unit that is connected to the control terminal of the first transistor and that renders the first transistor non-conductive in response to an input signal and to a second clock signal, the second clock signal having a phase lead by a half cycle or by one phase with respect to the first clock signal, with the plurality of clock signals constituting N-phase clocks, where N is an integer greater than or equal to two,
wherein the first transistor is connected between a first clock signal terminal at which the first clock signal is received and an output terminal at which the output signal is output,
the first control unit includes a second transistor that has a control terminal connected to an input terminal at which the input signal is received and that has one terminal connected to a control terminal of the first transistor, and
the second control unit includes:
a third transistor that has a control terminal connected to a second clock signal terminal at which the second clock signal is received;
a fourth transistor that is cascode connected to the third transistor;
a fifth transistor that is connected between the control terminal of the first transistor and a first power supply terminal;
a sixth transistor that is connected between the fourth transistor and the first power supply terminal and that has a control terminal connected to the input terminal;
a seventh transistor that is connected between the first power supply terminal and the output terminal and that has a control terminal connected to the connection node of the sixth transistor and the fourth transistor and also connected to a control terminal of the fifth transistor;
an eighth transistor that is connected between a control terminal of the fourth transistor and the first power supply terminal and that has a control terminal connected to the input terminal;
a ninth transistor that is diode-connected and connected between the control terminal of the fourth transistor and a second power supply terminal;
and
an eleventh transistor that is diode-connected and connected between the control terminal of the seventh transistor and a reset terminal at which a reset signal is received.

13 more elements

A bootstrap circuit which receives an input signal and a plurality of clock signals and generates an output signal, comprising:

a first transistor that receives a first clock signal and that, when in a conductive state, outputs the first clock signal as the output signal;
a first control unit that is connected to a control terminal of the first transistor and that renders the first transistor conductive, in response to the input signal;
and
a second control unit that is connected to the control terminal of the first transistor and that renders the first transistor non-conductive in response to an input signal and to a second clock signal, the second clock signal having a phase lead by a half cycle or by one phase with respect to the first clock signal, with the plurality of clock signals constituting N-phase clocks, where N is an integer greater than or equal to two,
wherein the first transistor is connected between a first clock signal terminal at which the first clock signal is received and an output terminal at which the output signal is output,
the first control unit includes a second transistor that has a control terminal connected to an input terminal at which the input signal is received and that has one terminal connected to a control terminal of the first transistor, and
the second control unit includes:
a third transistor that has a control terminal connected to a second clock signal terminal at which the second clock signal is received;
an inverter circuit that has an input connected to the input terminal;
a fourth transistor that is cascode connected to the third transistor and that has a control terminal connected to an output of the inverter circuit;
a fifth transistor that is connected between the control terminal of the first transistor and a power supply terminal;
a sixth transistor that is connected between the fourth transistor and the power supply terminal and that has a control terminal connected to the input terminal;
a seventh transistor that is connected between the power supply terminal and the output terminal and that has a control terminal connected to the connection node of the sixth transistor and the fourth transistor and also connected to a control terminal of the fifth transistor;
wherein the inverter circuit comprises:
an eighth transistor that is connected between a control terminal of the fourth transistor and the power supply terminal and that has a control terminal connected to the input terminal;
and
a ninth transistor that is diode-connected and connected between the control terminal of the fourth transistor and the first clock signal terminal.

14 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/470,788Filed 22 May 2009
Priority: JP 2008-13653126 May 2008
Published: US 2009/0290677 A126 Nov 2009
Granted: 15 Feb 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

Family

US 2009/0290677 A1Pre-grant publication · published 26 Nov 2009
US 7,889,832 B2This patent

From the US filing history. Foreign family members aren’t listed.

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