Process, voltage, temperature independent switched delay compensation scheme

A circuit for modeling a coarse delay element with a plurality of fine delay elements, the circuit comprising:

• first and second parallel delay paths for receiving a clock signal, the first path including
• a plurality of fine delay elements, and the second path including the same number of fine delay elements as the first path and a coarse delay element, each of the fine delay elements within the second path having a fixed delay for providing an output signal delayed relative to a received input signal by a constant duration of time;
• a phase detector for receiving the first and second clock delay signals from the first and second delay paths respectively, and for detecting a phase difference between the first and second clock delay signals;
• and
• a counter for receiving the phase difference from the phase detector and for generating a signal for adjusting a delay provided by the first delay path delay.

A delay lock loop (DLL) comprising a circuit for modeling a coarse delay element with a plurality of fine delay elements, the circuit comprising:

• first and second parallel delay paths for receiving a clock signal, the first path including a plurality of fine delay elements and the second path including the same number of fine delay elements as the first path and a coarse delay element, each of the fine delay elements within the second path having a fixed delay for providing an output signal delayed relative to a received input signal by a constant duration of time;
• a phase detector for receiving first and second clock delay signals from the first and second delay paths respectively, for detecting a phase difference between the first and second clock delay signals, and for providing the phase difference to a counter;
• and
• a decoder for receiving a signal from the counter, and for providing signals to the first delay path for adjusting a delay provided by the first delay path.