Methods for adjusting sampling clock of sampling circuit and related apparatuses

A method for adjusting a sampling clock of a sampling circuit, the method comprising:

• calculating a plurality of differences between adjacent sampled values of a plurality of sampled values, which are generated from the sampling circuit by sampling an incoming signal based on the sampling clock;
• performing a predetermined calculation on the plurality of differences to generate a calculated value, wherein the plurality of differences includes a first difference with a first absolute value and a second difference with a second absolute value less than the first absolute value, the calculated value is derived from at least a first portion and a second portion, the first portion is contributed by the first difference, the second portion is contributed by the second difference, and the predetermined calculation makes a first ratio of the first portion to the second portion greater than a second ratio of the first absolute value to the second absolute value;
• and
• adjusting a phase of the sampling clock so that the calculated value generated by the predetermined calculation satisfies a predetermined condition.

An analog-to-digital converting module capable of adaptively adjusting a phase of a sampling clock, the analog-to-digital converting module comprising:

• an analog-to-digital converter for sampling an incoming signal according to the sampling clock to generate a plurality of sampled values;
• a difference calculator coupled to the analog-to-digital converter for calculating a plurality of differences between adjacent sampled values;
• a computing unit coupled to the difference calculator for generating a calculated value according to the plurality of differences, which include a first difference with a first absolute value and a second difference with a second absolute value less than the first absolute value, wherein the calculated value is derived from at least a first portion and a second portion, the first portion is contributed by the first difference, the second portion is contributed by the second difference, and a first ratio of the first portion to the second portion is greater than a second ratio of the first absolute value to the second absolute value;
• and
• an adjusting circuit coupled to the computing unit and the analog-to-digital converter for adjusting the phase of the sampling clock so that the calculated value generated by the computing unit satisfies a predetermined condition.