Timing recovery in a parallel channel communication system
AssigneeSeagate Technology LLC
InventorsXueshi Yang, Mehmet F. Erden, Erozan M. Kurtas
Life of this patent
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Abstract
A parallel channel timing recovery circuit. The parallel timing recovery circuit comprises multiple prefilters receiving parallel channel outputs and providing prefilter outputs. Multiple sampling filters receive the prefilter outputs and provide multiple discrete time signal samples. A self-timing circuit has multiple inputs receiving the multiple discrete time signal samples. The self-timing circuit provides a sampling control output to the sampling filters. The sampling control output is based on a composite of the multiple discrete time signal samples. Each of the sampling filters generates a discrete time signal sample based on the sampling control output and the prefilter outputs.
Claims20
A parallel channel timing recovery circuit, comprising:
- an array of parallel read heads that provide parallel channel outputs of data;
- multiple prefilters receiving the parallel channel outputs and providing prefilter outputs;
- multiple sampling filters receiving the prefilter outputs and providing multiple discrete time signal samples;
- and
- a self-timing circuit that has multiple inputs receiving the multiple discrete time signal samples and that provides a sampling control output based on a linear transformation comprising coefficients that are adaptive for wear of the parallel read heads, the sampling control output coupling to the multiple sampling filters to control sampling.
A method of recovering timing for parallel channels, comprising:
- providing an array of parallel read heads that provide parallel channel outputs of data;
- providing multiple prefilters receiving the parallel channel outputs and providing prefilter outputs;
- sampling the prefilter outputs with sampling filters and providing multiple discrete time signal samples;
- and
- receiving the multiple discrete time signal samples at multiple inputs of a self-timing circuit and providing a sampling control output that is based on an adaptive linear transformation using adaptive coefficients and the sampling control output controlling sampling of the sampling filters;
- and
- generating the multiple discrete time signal samples based on the sampling control output.
A parallel channel timing recovery circuit, comprising:
- an array of parallel read heads that provide parallel channel outputs of data;
- multiple prefilters receiving the parallel channel outputs and providing prefilter outputs;
- multiple sampling filters receiving the prefilter outputs and providing multiple discrete time signal samples, each of the sampling filters including a sampling switch;
- and
- a self-timing circuit that receives the multiple discrete time signal samples at multiple inputs of the self-timing circuit and that provides a sampling control output that comprises a composite of the multiple discrete time signal samples combined into an adaptive linear transformation that controls each of the sampling switches.
Dependencies are inferred from the claim text.