Clock and data recovery circuit and communications apparatus including the clock and data recovery circuit

A communications apparatus comprising a clock and data recovery circuit,

• the clock and data recovery circuit comprising:
• a clock output unit configured to output N-phase clocks each of which has a phase shifted from the others by a time T2 obtained by dividing a period P1 of a reference clock at a receiver at a given frequency by N, where N is an integer equal to or greater than 3;
• a sampling unit configured to obtain sampling data serially transferred at every time T2;
• a first conversion unit configured to convert the sampling data into first N-bit parallel data every period P1;
• a second conversion unit configured to convert the first N-bit parallel data into second N-bit parallel data indicating a change point in the sampling data;
• and
• a data output unit configured to use the second N-bit parallel data as input of phase information and output third N-bit parallel data indicating substantially a center position of the change point in the sampling data,
• wherein data of the first N-bit parallel data at a position equal to substantially the center position indicated by the third N-bit parallel data is determined to be recovered data.