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US 7,889,778 B2Granted
Device for detecting an attack against an integrated circuit chip
AssigneeSTMicroelectronics S.r.l.
InventorsFabrice Marinet, Camille Botella
Life of this patent
Estimating the term…
Abstract
A circuit for detecting attacks by contacting an integrated circuit chip comprising means for applying a random signal to a first terminal of at least one conductive path formed in at least one first metallization level of the chip, means for comparing the applied signal with a signal present on a second terminal of the path, and means for delaying the comparison time with respect to the application time, of a duration longer than or equal to the propagation delay through the first path.
Claims15
A protection circuit, comprising:
- a signal generator operable to develop a security signal on an output node;
- a conductive path having an input node coupled to the output node of the signal generator and having an output node, the security signal applied on the input node being provided on the output node of the conductive path after a delay time;
- a comparison circuit coupled to the respective output nodes of the signal generator and the conductive path and operable to compare the signals on these output nodes only after a comparison time that is greater than the delay time, the comparison circuit being further operable to develop a comparison signal responsive to the comparison;
- and
- a trigger clock generator operable to develop a trigger clock signal having a period that is equal to or greater than the comparison time, and wherein the signal generator is operable to develop the security signal responsive to the trigger clock signal and wherein the comparison circuit is operable responsive to the trigger clock signal to compare the signals on the output nodes of the signal generator and the conductive path wherein the trigger clock signal generator includes a second conductive path that substantially determines the period of the trigger clock signal.
2 more elements
An electronic device, comprising:
- an electronic circuit including a protection circuit, the protection circuit including,
- a signal generator operable to develop a security signal on an output node;
- a conductive path having an input node coupled to the output node of the signal generator and having an output node, the security signal applied on the input node being provided on the output node of the conductive path after a delay time;
- and
- a comparison circuit coupled to the output nodes of the signal generator and the conductive path and adapted to receive a clocking signal, the comparison circuit operable responsive to the clocking signal to compare the signals on these output nodes only after a comparison time that is greater than or equal to the delay time, the clocking signal defining the comparison time and the comparison circuit being further operable to develop a comparison signal responsive to the comparison;
- and
- a trigger clock generator operable to develop a trigger clock signal having a period that is equal to or greater than the comparison time, and wherein the signal generator is operable to develop the security signal responsive to the trigger clock signal and wherein the comparison circuit is operable responsive to the trigger clock signal to compare the signals on the output nodes of the signal generator and the conductive path wherein the trigger clock signal generator includes a second conductive path that substantially determines the period of the trigger clock signal.
4 more elements
A method of detecting an attack to an integrated circuit, the method comprising:
- generating a security signal;
- delaying the security signal by a delay time to generate a delayed security signal;
- generating a clocking signal independent of the security signal and the delayed security signal;
- and
- responsive to the clocking signal, comparing the security signal and the delayed security signal, wherein the comparison interval is greater than or equal to the delay time;
- wherein generating the security signal occurs responsive to a trigger clock signal having a period that greater than or equal to the comparison interval, and wherein the operation of comparing occurs responsive to the trigger clock signal;
- and
- wherein delaying the security signal comprises applying the security signal through a conductive path and wherein the period of the trigger clock signal is applied through a second conductive path that substantially determines the period of the trigger clock signal.
5 more elements
Dependencies are inferred from the claim text.