Method of extending default fixed number of processing cycles in pipelined packet processor architecture

A packet processing system comprising:

• a processor;
• a plurality of commands, instructions, and/or state transitions;
• wherein the processor of the packet processing system to execute the plurality of commands, instructions, and/or state transitions causing the packet processing system to perform a method comprising:
• implementing a processing pipeline having a fixed number of processing cycles, the fixed number of processing cycles to be applied to each packet through the pipeline as a default fixed number of processing cycles;
• maintaining a count of a number of processing cycles performed or remaining for each packet relative to the default fixed number of processing cycles, wherein the count of the number of processing cycles performed or remaining for each packet is maintained within a FIFO (First In First Out) buffer of the packet processing system as state data within a pointer to the corresponding packet maintained in a separate and distinct FIFO buffer having the corresponding packet buffered therein;
• prior to completion of the default fixed number of processing cycles for each packet:
• determining whether processing is complete for the packet or whether extended processing is required for the packet,
• setting a DONE bit for the packet when processing is complete for the packet prior to completion of the default fixed number of processing cycles, and
• setting an extension bit when extended processing is required for the packet in excess of the default fixed number of processing cycles for the packet;
• exiting each packet from the processing pipeline having its respective DONE bit is set;
• allocating excess cycles in the processing pipeline for each packet exited from the processing pipeline due to having its respective DONE bit set, to one or more packets having their respective extension bit set indicating extended processing is required for the one or more packets;
• and
• applying the excess cycles in the processing pipeline to the extended processing required for each packet having its respective extension bit set, wherein the excess cycles are applied to each packet having its respective extension bit set through a subsequent cycle of the same processing pipeline.

A packet processing system comprising:

• a packet processor to implement a processing pipeline having a fixed number of processing cycles, the fixed number of processing cycles to be applied to each packet through the pipeline as a default fixed number of processing cycles wherein the packet processor is to:
• maintain a count of a number of processing cycles performed or remaining for each packet relative to the default fixed number of processing cycles, wherein the count of the number of processing cycles performed or remaining for each packet is maintained within a FIFO (First In First Out) buffer of the packet processing system as state data within a pointer to the corresponding packet maintained in a separate and distinct FIFO buffer having the corresponding packet buffered therein;
• determine, prior to completion of the default fixed number of processing cycles for each packet:
• whether processing is complete for the packet or whether extended processing is required for the packet,
• set a DONE bit for the packet when processing is complete for the packet prior to completion of the default fixed number of processing cycles, and
• set an extension bit when extended processing is required for the packet in excess of the default fixed number of processing cycles for the packet;
• wherein the packet processor is to further:
• exit each packet from the processing pipeline having its respective DONE bit is set;
• allocate excess cycles in the processing pipeline for each packet exited from the processing pipeline due to having its respective DONE bit set, to one or more packets having their respective extension bit set indicating extended processing is required for the one or more packets;
• and
• apply the excess cycles in the processing pipeline to the extended processing required for each packet having its respective extension bit set, wherein the excess cycles are applied to each packet having its respective extension bit set through a subsequent cycle of the same processing pipeline.