Switching circuit implementing variable string matching

#The present invention relates to the switching of Internet protocol (IP) packets. More specifically, the present invention relates to a content-aware switching application that examines the content of IP packets at non-deterministic locations, and switches the IP packets in response to the detected contents.

#Wide scale adoption of network-based applications is projected to occur over time, with tremendous increases in the number of Internet data centers deployed worldwide, and tens of billions of dollars in hosting revenue. Most data centers are not engineered to be reliable or scalable enough to support such growth. Transferring both dynamic and static content instantaneously within data centers will demand a whole new level of intelligence, power and control. Achieving quality of service (QoS) for application delivery from the data center will require more then just bandwidth and speed. Deeper visibility into IP traffic and application protocols at the transaction level will also be necessary. To address these issues, Internet data centers will have to replace limited, enterprise-class legacy platforms with new purpose-built hardware and software.

#FIG. 1 is a schematic diagram of a conventional TCP/IP packet 100. Packet 100 includes information designated layer 3 (L3), layer 4 (L4) and layer 7 (L7). Layer 3 includes a source address (SRC) 101 and a destination address (DST) 102. Layer 4 includes a source port identifier 103 and a destination port identifier 104. Layers 3 and 4 are located at deterministic locations of IP packet 100. Thus, it is relatively easy to locate and extract the information in Layers 3 and 4. As a result, most routing switches operate on the information present in Layers 3 and 4. However, as described above, it will become difficult, if not impossible, to switch packets at high speeds (OC-48, OC-192) based on Layers 3 and 4 as the number of Internet data centers increase.

#FIG. 1 is a schematic drawing of a conventional Internet protocol packet.

#FIG. 2 is a block diagram of a content matching engine (CME) in accordance with one embodiment of the present invention.

#FIG. 3 is a block diagram of a system that uses the CME of FIG. 2 in accordance with one embodiment of the present invention.

#FIG. 2 is a block diagram of a content matching engine (CME) 200 in accordance with one embodiment of the present invention. CME 200 has an input port for receiving packet data at a 2.4 Gbps (OC-48) or a 10 Gbps rate (OC-192). CME 200 also has an input port for receiving a set of rules, which are stored in CME 200. CME 200 determines whether each incoming packet matches any of the rules. If CME 200 determines that a match exists, then CME 200 asserts a MATCH signal and provides an INDEX signal associated with the matched rule.

#FIG. 3 is a block diagram of a system 300 that uses CME 200. In addition to CME 200, system 300 includes control processor 301, network processing unit (NPU)/ASIC 302 and framer/PHY 303. Control processor 301 loads the rules into CME 200. Control processor 301 also loads instructions into NPU/ASIC 302. These instructions define the manner in which NPU/ASIC 302 processes a received packet when the received packet matches one of the rules. Framer/PHY 303 receives and aligns data packets from a fiber-optic network, and provides the aligned data packets to CME 200 and NPU/ASIC 302. If CME 200 determines that a received packet matches one of the rules, CME 200 asserts the MATCH signal and provides an INDEX value associated with the matched rule to NPU/ASIC 302. In response to the MATCH/INDEX signals, NPU/ASIC 302 routes the packet through a switch fabric to an output port, which is designed to efficiently process the packet in view of the matched rule.

#FIG. 4 is a block diagram of an alternate system 400 that uses CME 200. In addition to CME 200, system 400 includes control processor 401, network processing unit (NPU)/ASIC 402 and framer/PHY 403. System 400 is controlled in a manner similar to system 300. However, system 400 uses quad data rate (QDR) packets, whereas system 300 uses a SPI3 or SPI4.2 style packet interface.