Semiconductor memory device
AssigneeHynix Semiconductor Inc.
InventorJung-Hoon Park
Life of this patent
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Abstract
A semiconductor memory device includes a clock inputting unit configured to receive a system clock and a data clock, a clock dividing unit configured to divide a frequency of the data clock to generate a data division clock and determining a phase of the data division clock according to a division control signal, a phase dividing unit configured to generate a plurality of multiple-phase data division clocks each having a predetermined phase difference according to the data division clock, and a first phase detecting unit configured to detect a phase of the system clock based on a predetermined selection clock among the multiple-phase data division clocks, and generate the division control signal according to the detection result.
Claims35
A semiconductor memory device, comprising:
- a clock inputting unit configured to generate a system clock and a data clock;
- a clock dividing unit configured to generate a data division clock by dividing a frequency of the data clock and to determine a phase of the data division clock according to a division control signal;
- a phase dividing unit configured to generate a plurality of multiple-phase data division clocks, each of which has a predetermined phase difference according to the data division clock;
- and
- a first phase detecting unit configured to detect a phase of the system clock based on a predetermined selection clock among the multiple-phase data division clocks, and generate the division control signal according to the detection result.
An operation method of a semiconductor memory device, the operation method comprising:
- receiving a system clock and a data clock;
- dividing a frequency of the data clock to generate a data division clock, wherein a phase of the data division clock is determined according to a division control signal;
- sensing an entry of a normal training mode or an entry of an auto training mode;
- generating a plurality of multiple-phase data division clocks having respective predetermined phase differences according to the data division clock when the auto training mode is entered according to the sensing result;
- and
- detecting a phase of the system clock and a phase of a predetermined selection clock among the multiple-phase data division clocks, and determining a logic level of the division control signal according to the detecting result.
Dependencies are inferred from the claim text.